{"id":"https://openalex.org/W2163358310","doi":"https://doi.org/10.1145/1120725.1120783","title":"A practical cut-based physical retiming algorithm for field programmable gate arrays","display_name":"A practical cut-based physical retiming algorithm for field programmable gate arrays","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2163358310","doi":"https://doi.org/10.1145/1120725.1120783","mag":"2163358310"},"language":"en","primary_location":{"id":"doi:10.1145/1120725.1120783","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120783","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063606966","display_name":"Peter Suaris","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter Suaris","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100450580","display_name":"Dongsheng Wang","orcid":"https://orcid.org/0000-0001-7676-7767"},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dongsheng Wang","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060536841","display_name":"Nan-Chi Chou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nan-Chi Chou","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR","institution_ids":["https://openalex.org/I4210156212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210156212"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21638108,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1027","last_page":"1027"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.9832779765129089},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7277916669845581},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.718543291091919},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5397790670394897},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5211098790168762},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4975874722003937},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4889313280582428},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.4704662263393402},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46642833948135376},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4340147376060486},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.39565443992614746},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2577962875366211},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.06951349973678589}],"concepts":[{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.9832779765129089},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7277916669845581},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.718543291091919},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5397790670394897},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5211098790168762},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4975874722003937},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4889313280582428},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.4704662263393402},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46642833948135376},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4340147376060486},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.39565443992614746},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2577962875366211},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.06951349973678589}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1120725.1120783","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120783","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2013815172","https://openalex.org/W2063146554","https://openalex.org/W2096869104","https://openalex.org/W2120060202","https://openalex.org/W2124054952","https://openalex.org/W2142605272","https://openalex.org/W2148631003","https://openalex.org/W2152362440","https://openalex.org/W2157398460"],"related_works":["https://openalex.org/W4246197519","https://openalex.org/W4251323573","https://openalex.org/W2142361597","https://openalex.org/W4252245464","https://openalex.org/W2127580684","https://openalex.org/W1984491986","https://openalex.org/W2100249453","https://openalex.org/W4252511707","https://openalex.org/W2135636985","https://openalex.org/W2163358310"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,82],"heuristic":[4],"cut-based":[5],"retiming":[6,14,92],"algorithm":[7,36,68],"for":[8],"FPGA":[9,74],"designs.":[10],"It":[11],"handles":[12],"complex":[13,61],"constraints":[15],"including":[16],"timing,":[17],"architectural":[18],"and":[19,28],"structural":[20],"constraints;":[21],"improves":[22,37],"retimeability":[23],"by":[24,40,76],"incorporating":[25],"logic":[26,53],"resynthesis;":[27],"efficiently":[29],"integrates":[30],"with":[31,90],"incremental":[32],"placement.":[33],"Thus,":[34],"the":[35,55,71],"timing":[38],"compliance":[39],"allowing":[41],"groups":[42],"of":[43,51,73,87],"registers":[44],"to":[45],"be":[46],"rapidly":[47],"retimed":[48],"across":[49],"blocks":[50],"combinational":[52],"in":[54,85],"physical":[56],"domain":[57],"without":[58],"violating":[59],"any":[60],"constraints.":[62],"Experiments":[63],"have":[64],"shown":[65],"that":[66],"this":[67],"can":[69],"improve":[70],"performance":[72],"designs":[75],"16%":[77],"on":[78],"average,":[79],"while":[80],"achieving":[81],"61.7%":[83],"speedup":[84],"terms":[86],"runtime":[88],"compared":[89],"classic":[91],"algorithms.":[93]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}