{"id":"https://openalex.org/W2090344586","doi":"https://doi.org/10.1145/1120725.1120780","title":"Integrated algorithmic logical and physical design of integer multiplier","display_name":"Integrated algorithmic logical and physical design of integer multiplier","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2090344586","doi":"https://doi.org/10.1145/1120725.1120780","mag":"2090344586"},"language":"en","primary_location":{"id":"doi:10.1145/1120725.1120780","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120780","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012203443","display_name":"Shuo Zhou","orcid":"https://orcid.org/0000-0002-6323-8222"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shuo Zhou","raw_affiliation_strings":["University of California at San Diego, La Jolla, CA","Comput. Sci. & Eng., California Univ., La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California at San Diego, La Jolla, CA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"Comput. Sci. & Eng., California Univ., La Jolla, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025550960","display_name":"Bo Yao","orcid":"https://orcid.org/0009-0002-2225-9956"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bo Yao","raw_affiliation_strings":["University of California at San Diego, La Jolla, CA","Comput. Sci. & Eng., California Univ., La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California at San Diego, La Jolla, CA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"Comput. Sci. & Eng., California Univ., La Jolla, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100405315","display_name":"Jianhua Liu","orcid":"https://orcid.org/0000-0001-7492-6242"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jian-Hua Liu","raw_affiliation_strings":["University of California at San Diego, La Jolla, CA","Comput. Sci. & Eng., California Univ., La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California at San Diego, La Jolla, CA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"Comput. Sci. & Eng., California Univ., La Jolla, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111503558","display_name":"Chung-Kuan Cheng","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chung-Kuan Cheng","raw_affiliation_strings":["University of California at San Diego, La Jolla, CA","Comput. Sci. & Eng., California Univ., La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California at San Diego, La Jolla, CA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"Comput. Sci. & Eng., California Univ., La Jolla, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1014","last_page":"1014"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.8657143115997314},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5660159587860107},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44653382897377014},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4411256015300751},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3825373947620392},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3558619022369385},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3080749809741974},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2300117015838623},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.22224697470664978},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.10668224096298218}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.8657143115997314},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5660159587860107},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44653382897377014},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4411256015300751},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3825373947620392},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3558619022369385},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3080749809741974},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2300117015838623},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.22224697470664978},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.10668224096298218},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1120725.1120780","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120780","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1580879576","https://openalex.org/W1594843402","https://openalex.org/W1983849809","https://openalex.org/W2012206984","https://openalex.org/W2097181398","https://openalex.org/W2097716881","https://openalex.org/W2107088801","https://openalex.org/W2111659225","https://openalex.org/W2117453169","https://openalex.org/W2133110406","https://openalex.org/W2149565956","https://openalex.org/W2154098113","https://openalex.org/W2159552109","https://openalex.org/W3127394485"],"related_works":["https://openalex.org/W4281295723","https://openalex.org/W2121036163","https://openalex.org/W2102547348","https://openalex.org/W4247095439","https://openalex.org/W2146286671","https://openalex.org/W2098419840","https://openalex.org/W2110969704","https://openalex.org/W1966764473","https://openalex.org/W4238844454","https://openalex.org/W2118796996"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"integrated":[4],"methodology":[5],"for":[6,75,81],"high-performance":[7],"integer":[8],"multiplier":[9,47],"design,":[10],"which":[11,29],"combines":[12],"algorithmic":[13],"partial":[14],"product":[15],"generation,":[16],"logic":[17],"synthesis,":[18],"and":[19,79],"physical":[20],"layout":[21],"into":[22],"a":[23,34,64,76,82],"unified":[24],"process.":[25],"The":[26,42],"interconnect":[27],"delay,":[28],"dominates":[30],"the":[31,46,52,56,67],"performance":[32],"of":[33,55,70],"multiplier,":[35,78],"is":[36],"thoroughly":[37],"considered":[38],"in":[39,45],"this":[40],"integration.":[41],"special":[43],"structures":[44],"are":[48,73],"utilized":[49],"to":[50],"reduce":[51],"high":[53],"complexity":[54],"holistic":[57],"approach.":[58],"Compared":[59],"with":[60],"multipliers":[61],"generated":[62],"by":[63],"state-of-the-art":[65],"tool,":[66],"timing":[68],"improvements":[69],"our":[71],"results":[72],"11%":[74],"16-bit":[77],"7.5%":[80],"32-bit":[83],"multiplier.":[84]},"counts_by_year":[],"updated_date":"2026-07-19T07:52:34.831488","created_date":"2025-10-10T00:00:00"}