{"id":"https://openalex.org/W2164734753","doi":"https://doi.org/10.1145/1120725.1120778","title":"Design and design automation of rectification logic for engineering change","display_name":"Design and design automation of rectification logic for engineering change","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2164734753","doi":"https://doi.org/10.1145/1120725.1120778","mag":"2164734753"},"language":"en","primary_location":{"id":"doi:10.1145/1120725.1120778","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019119010","display_name":"Cheng-Hung Lin","orcid":"https://orcid.org/0000-0001-9254-9751"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Cheng-Hung Lin","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062636233","display_name":"Yung-Chang Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Chang Huang","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073382186","display_name":"Shih-Chieh Chang","orcid":"https://orcid.org/0000-0003-0717-6466"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shih-Chieh Chang","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110090558","display_name":"Wen-Ben Jone","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wen-Ben Jone","raw_affiliation_strings":["University of Cincinnati, Cincinnati, Ohio"],"affiliations":[{"raw_affiliation_string":"University of Cincinnati, Cincinnati, Ohio","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5019119010"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":0.7916,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.76313079,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1006","last_page":"1006"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/rectification","display_name":"Rectification","score":0.6145532727241516},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.6098564267158508},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5490813255310059},{"id":"https://openalex.org/keywords/computer-automated-design","display_name":"Computer-automated design","score":0.5411337018013},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5049462914466858},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4121389389038086},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3257724940776825},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2720727324485779},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.24061843752861023},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15326809883117676},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15205684304237366},{"id":"https://openalex.org/keywords/systems-design","display_name":"Systems design","score":0.1220194399356842},{"id":"https://openalex.org/keywords/mechanical-engineering","display_name":"Mechanical engineering","score":0.11487671732902527}],"concepts":[{"id":"https://openalex.org/C50942859","wikidata":"https://www.wikidata.org/wiki/Q4967193","display_name":"Rectification","level":3,"score":0.6145532727241516},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.6098564267158508},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5490813255310059},{"id":"https://openalex.org/C205976826","wikidata":"https://www.wikidata.org/wiki/Q5157390","display_name":"Computer-automated design","level":3,"score":0.5411337018013},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5049462914466858},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4121389389038086},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3257724940776825},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2720727324485779},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.24061843752861023},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15326809883117676},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15205684304237366},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.1220194399356842},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.11487671732902527},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1120725.1120778","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.113.7438","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.113.7438","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cad63.cs.nthu.edu.tw/publications/lib/exe/fetch.php?id=shih-chieh chang&cache=cache&media=design_and_design_automation_of_rectification_logic_for_engineering_change.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2097293815","https://openalex.org/W2109092163","https://openalex.org/W2137636909","https://openalex.org/W2155220566","https://openalex.org/W2157030859","https://openalex.org/W2158753855","https://openalex.org/W2164038636","https://openalex.org/W2295683841"],"related_works":["https://openalex.org/W2024555067","https://openalex.org/W2038083073","https://openalex.org/W2098419840","https://openalex.org/W2019954703","https://openalex.org/W2046521720","https://openalex.org/W1966764473","https://openalex.org/W2171793444","https://openalex.org/W4376311825","https://openalex.org/W2148101730","https://openalex.org/W2789349722"],"abstract_inverted_index":{"In":[0,29,50],"a":[1,5,14,55,60,77],"later":[2],"stage":[3],"of":[4,42,128],"VLSI":[6],"design,":[7],"it":[8],"is":[9,79],"quite":[10],"often":[11],"to":[12,17,25,31,58,64,70,87,132],"modify":[13],"design":[15,22,27,34],"implementation":[16,131],"accommodate":[18],"the":[19,33,37,40,43,66,72,84,89,110,114,129],"new":[20,38,56,90],"specification,":[21],"errors,":[23],"or":[24,104],"meet":[26,32],"constraints.":[28],"addition":[30],"schedule":[35],"for":[36,113],"implementation,":[39],"reduction":[41],"mask":[44,67,100],"set":[45],"have":[46],"become":[47,133],"very":[48,144],"critical.":[49],"this":[51],"paper,":[52],"we":[53,117],"propose":[54,119],"method":[57],"add":[59],"programmable":[61,101],"rectification":[62,85,93,115],"module":[63,86,94],"reduce":[65,109],"cost":[68],"and":[69,137],"improve":[71],"turn":[73],"around":[74],"time.":[75],"When":[76],"modification":[78],"needed,":[80],"one":[81,99],"can":[82,95,122],"program":[83],"achieve":[88],"implementation.":[91],"The":[92],"be":[96],"designed":[97],"by":[98],"gate":[102],"array,":[103],"an":[105],"embedded":[106],"FPGA.":[107],"To":[108],"size":[111],"needed":[112],"module,":[116],"also":[118],"algorithms,":[120],"which":[121],"intelligently":[123],"select":[124],"some":[125],"internal":[126],"signals":[127],"old":[130],"pseudo":[134],"primary":[135,138],"inputs":[136],"outputs.":[139],"Our":[140],"experimental":[141],"results":[142],"are":[143],"encouraging.":[145]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}