{"id":"https://openalex.org/W2040514393","doi":"https://doi.org/10.1145/1119772.1119959","title":"Graph matching-based algorithms for array-based FPGA segmentation design and routing","display_name":"Graph matching-based algorithms for array-based FPGA segmentation design and routing","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2040514393","doi":"https://doi.org/10.1145/1119772.1119959","mag":"2040514393"},"language":"en","primary_location":{"id":"doi:10.1145/1119772.1119959","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119959","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058023716","display_name":"Jai-Ming Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I901624438","display_name":"Realtek (Taiwan)","ror":"https://ror.org/05x1ffr83","country_code":"TW","type":"company","lineage":["https://openalex.org/I901624438"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Jai-Ming Lin","raw_affiliation_strings":["Realtek Semiconductor Corp., Hsinchu, Taiwan","Realtek Semicond. Corp., Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Realtek Semiconductor Corp., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438"]},{"raw_affiliation_string":"Realtek Semicond. Corp., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031111194","display_name":"Song-Ra Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I1334877674","display_name":"Taiwan Semiconductor Manufacturing Company (United States)","ror":"https://ror.org/02rvfjx92","country_code":"US","type":"company","lineage":["https://openalex.org/I1334877674","https://openalex.org/I4210120917"]},{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW","US"],"is_corresponding":false,"raw_author_name":"Song-Ra Pan","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan","[Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan.]"],"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]},{"raw_affiliation_string":"[Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan.]","institution_ids":["https://openalex.org/I1334877674"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan","National Taiwan University Taipei,Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"National Taiwan University Taipei,Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5058023716"],"corresponding_institution_ids":["https://openalex.org/I901624438"],"apc_list":null,"apc_paid":null,"fwci":0.7083,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.72060584,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"851","last_page":"851"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7162148952484131},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7112200260162354},{"id":"https://openalex.org/keywords/segmentation","display_name":"Segmentation","score":0.5352715849876404},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5071446895599365},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.48428863286972046},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4563712179660797},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.44454121589660645},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4331158399581909},{"id":"https://openalex.org/keywords/routing-algorithm","display_name":"Routing algorithm","score":0.4320671558380127},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.29565221071243286},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2124628722667694},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1481589674949646},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14445316791534424},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.08346489071846008}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7162148952484131},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7112200260162354},{"id":"https://openalex.org/C89600930","wikidata":"https://www.wikidata.org/wiki/Q1423946","display_name":"Segmentation","level":2,"score":0.5352715849876404},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5071446895599365},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.48428863286972046},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4563712179660797},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.44454121589660645},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4331158399581909},{"id":"https://openalex.org/C2984173633","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Routing algorithm","level":4,"score":0.4320671558380127},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.29565221071243286},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2124628722667694},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1481589674949646},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14445316791534424},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.08346489071846008},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1119772.1119959","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119959","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.387.6329","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.6329","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/09b_5.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.97.2112","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.97.2112","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cc.ee.ntu.edu.tw/~ywchang/Papers/aspdac03-fpga.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W60769399","https://openalex.org/W1523051745","https://openalex.org/W1910202155","https://openalex.org/W1973310391","https://openalex.org/W1975756407","https://openalex.org/W1983950263","https://openalex.org/W2007049691","https://openalex.org/W2030542050","https://openalex.org/W2040455347","https://openalex.org/W2053913299","https://openalex.org/W2101302701","https://openalex.org/W2113669717","https://openalex.org/W2116349445","https://openalex.org/W2117492357","https://openalex.org/W2124231236","https://openalex.org/W2125690626","https://openalex.org/W2125990954","https://openalex.org/W2131385043","https://openalex.org/W2132275486","https://openalex.org/W2134066224","https://openalex.org/W2139637699","https://openalex.org/W2143244742","https://openalex.org/W2143274385","https://openalex.org/W2156134305","https://openalex.org/W2160474882","https://openalex.org/W3023861350","https://openalex.org/W3147517101"],"related_works":["https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2184011203","https://openalex.org/W2149224531","https://openalex.org/W4247716783","https://openalex.org/W2160885658","https://openalex.org/W2098791961","https://openalex.org/W2144164383","https://openalex.org/W4230539218","https://openalex.org/W2137646787"],"abstract_inverted_index":{"Architecture":[0],"and":[1,16,47,56,71,126,141],"CAD":[2],"are":[3],"closely":[4],"related":[5],"issues":[6],"in":[7,113,129,135],"FPGA":[8,54],"design.":[9,58],"Routing":[10],"architecture":[11],"design":[12,25],"shall":[13,26],"optimize":[14,35],"routability":[15],"facilitate":[17],"router":[18,24,84],"development;":[19],"on":[20,123],"the":[21,28,36,39,60,65,78,83,136,142],"other":[22],"hand,":[23],"consider":[27,64,95],"specific":[29],"properties":[30],"of":[31,38,67,99],"routing":[32,55,69,91,100],"architectures":[33],"to":[34,76],"performance":[37],"router.":[40],"In":[41],"this":[42],"paper,":[43],"we":[44,63,86],"propose":[45],"effective":[46],"efficient":[48],"unified":[49],"matching-based":[50,89],"algorithms":[51],"for":[52],"array-based":[53],"segmentation":[57,61,80],"For":[59,82,117],"design,":[62,85],"similarity":[66],"input":[68],"instances":[70],"formulate":[72],"a":[73,88,96],"net-matching":[74],"problem":[75],"construct":[77],"optimal":[79],"architecture.":[81],"present":[87],"timing-driven":[90],"algorithm":[92],"which":[93],"can":[94],"versatile":[97],"set":[98],"segments.":[101],"Experimental":[102],"results":[103],"show":[104],"that":[105],"our":[106,119],"designed":[107,120],"segmentations":[108,121],"significantly":[109],"outperform":[110],"those":[111,133],"used":[112,134],"commercially":[114],"available":[115],"FPGAs.":[116],"example,":[118],"achieve,":[122],"average,":[124],"14.6%":[125],"19.7%":[127],"improvements":[128],"routability,":[130],"compared":[131],"with":[132],"Lucent":[137],"Technologies":[138],"ORCA":[139],"2C-series":[140],"Xilinx":[143],"XC4000E-series":[144],"FPGAs,":[145],"respectively.":[146]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
