{"id":"https://openalex.org/W2037924734","doi":"https://doi.org/10.1145/1119772.1119953","title":"Integer linear programming-based synthesis of skewed logic circuits","display_name":"Integer linear programming-based synthesis of skewed logic circuits","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2037924734","doi":"https://doi.org/10.1145/1119772.1119953","mag":"2037924734"},"language":"en","primary_location":{"id":"doi:10.1145/1119772.1119953","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108484594","display_name":"Aiqun Cao","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Aiqun Cao","raw_affiliation_strings":["Purdue University","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066002757","display_name":"Naran Sirisantana","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Naran Sirisantana","raw_affiliation_strings":["Purdue University","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110204557","display_name":"Cheng\u2010Kok Koh","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheng-Kok Koh","raw_affiliation_strings":["Purdue University","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0009-0002-3375-2877"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["Purdue University","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5108484594"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":0.354,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.62801657,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"820","last_page":"820"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.7838060259819031},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.6889562606811523},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5627763867378235},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5574623346328735},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5505068302154541},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5366626977920532},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5218485593795776},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.44695553183555603},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42954784631729126},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4282037615776062},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.38850679993629456},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0915137529373169},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06287097930908203}],"concepts":[{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.7838060259819031},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.6889562606811523},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5627763867378235},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5574623346328735},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5505068302154541},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5366626977920532},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5218485593795776},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.44695553183555603},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42954784631729126},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4282037615776062},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.38850679993629456},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0915137529373169},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06287097930908203}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1119772.1119953","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.151.3206","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.151.3206","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://dynamo.ecn.purdue.edu/~chengkok/papers/2003/p820-cao.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.387.4690","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.4690","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/09a_4.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1505910485","https://openalex.org/W1894566516","https://openalex.org/W2113386515","https://openalex.org/W2130804120","https://openalex.org/W2145606027","https://openalex.org/W2149966501","https://openalex.org/W2166278197"],"related_works":["https://openalex.org/W2082788688","https://openalex.org/W1488117239","https://openalex.org/W3129977055","https://openalex.org/W1894566516","https://openalex.org/W1966764473","https://openalex.org/W2386022279","https://openalex.org/W2991771859","https://openalex.org/W2149966501","https://openalex.org/W4248475372","https://openalex.org/W2370649629"],"abstract_inverted_index":{"We":[0],"present":[1],"an":[2,48],"integer":[3],"linear":[4],"programming-based":[5],"approach":[6],"for":[7],"solving":[8],"the":[9,29,32,38],"logic":[10,15,19,59,65,75],"reconvergence":[11],"problem":[12,34],"in":[13,57,63],"skewed":[14,58],"circuits":[16,66,76],"with":[17],"minimal":[18],"duplication":[20],"cost.":[21],"A":[22],"simplification":[23],"technique":[24],"is":[25,41,77],"applied":[26],"to":[27],"reduce":[28],"complexity":[30],"of":[31,50,52],"ILP":[33],"greatly":[35],"so":[36],"that":[37,47],"run":[39],"time":[40],"more":[42],"affordable.":[43],"Experimental":[44],"results":[45],"show":[46],"average":[49,70],"18%":[51],"original":[53],"gates":[54],"are":[55,67],"duplicated":[56],"circuits,":[60],"whereas":[61],"65%":[62],"Domino":[64,74],"duplicated.":[68],"The":[69],"power":[71],"saving":[72],"over":[73],"40.9%.":[78]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
