{"id":"https://openalex.org/W2030889972","doi":"https://doi.org/10.1145/1119772.1119943","title":"An automated method for test model generation from switch level circuits","display_name":"An automated method for test model generation from switch level circuits","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2030889972","doi":"https://doi.org/10.1145/1119772.1119943","mag":"2030889972"},"language":"en","primary_location":{"id":"doi:10.1145/1119772.1119943","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119943","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077215997","display_name":"Tim McDougall","orcid":"https://orcid.org/0000-0002-9843-9315"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Tim McDougall","raw_affiliation_strings":["Motorola Inc., Mawson Lakes, South Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Motorola Inc., Mawson Lakes, South Australia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045630735","display_name":"Atanas Parashkevov","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Atanas Parashkevov","raw_affiliation_strings":["Motorola Inc., Mawson Lakes, South Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Motorola Inc., Mawson Lakes, South Australia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009827531","display_name":"S. Jolly","orcid":"https://orcid.org/0000-0002-2713-0732"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Simon Jolly","raw_affiliation_strings":["Foursticks Pty. Ltd., Frewville, South Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Foursticks Pty. Ltd., Frewville, South Australia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076928586","display_name":"Juhong Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Juhong Zhu","raw_affiliation_strings":["Motorola Inc., Austin, TX","Motorola Inc. Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Motorola Inc., Austin, TX","institution_ids":["https://openalex.org/I1333370159"]},{"raw_affiliation_string":"Motorola Inc. Austin, TX","institution_ids":["https://openalex.org/I1333370159"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100747916","display_name":"Jing Zeng","orcid":"https://orcid.org/0009-0000-4100-5869"},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jing Zeng","raw_affiliation_strings":["Motorola Inc., Austin, TX","Motorola Inc. Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Motorola Inc., Austin, TX","institution_ids":["https://openalex.org/I1333370159"]},{"raw_affiliation_string":"Motorola Inc. Austin, TX","institution_ids":["https://openalex.org/I1333370159"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005302919","display_name":"C. Pyron","orcid":null},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carol Pyron","raw_affiliation_strings":["Motorola Inc., Austin, TX","Motorola Inc. Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Motorola Inc., Austin, TX","institution_ids":["https://openalex.org/I1333370159"]},{"raw_affiliation_string":"Motorola Inc. Austin, TX","institution_ids":["https://openalex.org/I1333370159"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011349515","display_name":"Magdy S. Abadir","orcid":"https://orcid.org/0000-0003-4046-2472"},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Magdy Abadir","raw_affiliation_strings":["Motorola Inc., Austin, TX","Motorola Inc. Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Motorola Inc., Austin, TX","institution_ids":["https://openalex.org/I1333370159"]},{"raw_affiliation_string":"Motorola Inc. Austin, TX","institution_ids":["https://openalex.org/I1333370159"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5077215997"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4955,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.65007485,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"769","last_page":"769"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7757577896118164},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7189340591430664},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6861532330513},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5678486227989197},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5562481880187988},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4935060739517212},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4932858347892761},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4873853325843811},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4837465286254883},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4480644464492798},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4392821788787842},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3674218952655792},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3311799466609955},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21483248472213745},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16060450673103333},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14789870381355286}],"concepts":[{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7757577896118164},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7189340591430664},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6861532330513},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5678486227989197},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5562481880187988},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4935060739517212},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4932858347892761},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4873853325843811},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4837465286254883},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4480644464492798},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4392821788787842},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3674218952655792},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3311799466609955},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21483248472213745},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16060450673103333},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14789870381355286},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1119772.1119943","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119943","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.387.8153","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.8153","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/08c_4.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6800000071525574,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1833620934","https://openalex.org/W2010065567","https://openalex.org/W2106695788","https://openalex.org/W2150985480"],"related_works":["https://openalex.org/W4254560580","https://openalex.org/W2131559056","https://openalex.org/W2127167802","https://openalex.org/W2080984854","https://openalex.org/W2323083271","https://openalex.org/W4283025278","https://openalex.org/W2019500818","https://openalex.org/W2082432309","https://openalex.org/W1600330381","https://openalex.org/W4308651027"],"abstract_inverted_index":{"Custom":[0],"VLSI":[1],"design":[2],"at":[3,73,103],"the":[4,48,74,95,116,127],"switch":[5,38,49,75,90],"level":[6,30,39,50,68,91,106],"is":[7,13,119],"commonly":[8],"applied":[9],"when":[10],"a":[11,104],"chip":[12],"required":[14],"to":[15,93,133],"meet":[16,126],"stringent":[17],"operating":[18],"requirements":[19,129],"in":[20],"terms":[21],"of":[22,97,107,121],"speed,":[23],"power,":[24],"or":[25],"area.":[26],"ATPG":[27,128],"requires":[28],"gate":[29,67,123],"models,":[31],"which":[32,87,113],"are":[33,44,131],"verified":[34],"for":[35,65],"correctness":[36],"against":[37],"models.":[40],"Typically,":[41],"test":[42,69],"models":[43,70,124],"created":[45,135],"manually":[46,134],"from":[47,71],"models---a":[51],"tedious,":[52],"error-prone":[53],"process":[54],"requiring":[55],"experienced":[56],"DFT":[57],"engineers.":[58],"This":[59],"paper":[60],"presents":[61],"an":[62],"automated":[63,117],"flow":[64,79,118],"creating":[66],"circuits":[72],"level.":[76],"The":[77],"proposed":[78],"utilizes":[80],"Motorola's":[81],"Switch":[82],"Level":[83],"Verification":[84],"(SLV)":[85],"tool,":[86],"employs":[88],"detailed":[89],"analysis":[92],"model":[94],"behavior":[96],"MOS":[98],"transistors":[99],"and":[100,130],"represent":[101],"them":[102],"higher":[105],"abstraction.":[108],"We":[109],"present":[110],"experimental":[111],"results,":[112],"demonstrate":[114],"that":[115,125],"capable":[120],"producing":[122],"comparable":[132],"ones.":[136]},"counts_by_year":[],"updated_date":"2026-05-05T08:41:31.759640","created_date":"2025-10-10T00:00:00"}