{"id":"https://openalex.org/W2043443884","doi":"https://doi.org/10.1145/1119772.1119919","title":"Efficient loop-back testing of on-chip ADCs and DACs","display_name":"Efficient loop-back testing of on-chip ADCs and DACs","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2043443884","doi":"https://doi.org/10.1145/1119772.1119919","mag":"2043443884"},"language":"en","primary_location":{"id":"doi:10.1145/1119772.1119919","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119919","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111875390","display_name":"Hak-soo Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hak-soo Yu","raw_affiliation_strings":["Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jacob A. Abraham","raw_affiliation_strings":["Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112799931","display_name":"Sungbae Hwang","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sungbae Hwang","raw_affiliation_strings":["Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010398207","display_name":"Jeongjin Roh","orcid":"https://orcid.org/0000-0001-6930-8183"},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jeongjin Roh","raw_affiliation_strings":[", Hanyang University, , Korea"],"affiliations":[{"raw_affiliation_string":", Hanyang University, , Korea","institution_ids":["https://openalex.org/I4575257"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5111875390"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":0.8814,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.74163951,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"651","last_page":"651"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5943767428398132},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5359134674072266},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5278090238571167},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.476631760597229},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.45286932587623596},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4132130742073059},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21318981051445007},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.18376493453979492},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17671534419059753},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12017756700515747},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09900772571563721}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5943767428398132},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5359134674072266},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5278090238571167},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.476631760597229},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.45286932587623596},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4132130742073059},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21318981051445007},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.18376493453979492},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17671534419059753},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12017756700515747},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09900772571563721},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1119772.1119919","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119919","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W118952169","https://openalex.org/W1494738794","https://openalex.org/W1580014081","https://openalex.org/W1857383444","https://openalex.org/W2101752872","https://openalex.org/W2109911518","https://openalex.org/W2153660465","https://openalex.org/W2184277408"],"related_works":["https://openalex.org/W2352076433","https://openalex.org/W1975856998","https://openalex.org/W2536291958","https://openalex.org/W1996400816","https://openalex.org/W2148421408","https://openalex.org/W2088830176","https://openalex.org/W2117760489","https://openalex.org/W1906153017","https://openalex.org/W2540196010","https://openalex.org/W2356774932"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"efficient":[4],"approach":[5,53],"to":[6,10,16,31,77],"testing":[7],"on-chip":[8],"analog":[9,17],"digital":[11,15,24],"converters":[12,18,74],"(ADCs)":[13],"and":[14,47,56],"(DACs)":[19],"in":[20],"loop-back":[21,65],"mode.":[22],"On-chip":[23],"signal":[25],"processing":[26],"units":[27],"can":[28],"be":[29],"used":[30],"generate":[32],"stimuli.":[33],"With":[34],"this":[35],"methodology,":[36],"go/no-go":[37],"tests":[38],"as":[39,41],"well":[40],"characterization":[42],"of":[43,63,72,81],"the":[44,58,79,82],"individual":[45],"ADCs":[46],"DACs":[48],"are":[49,75],"possible.":[50],"The":[51],"proposed":[52],"is":[54],"simple":[55],"overcomes":[57],"low":[59],"parametric":[60],"fault":[61],"coverage":[62],"conventional":[64],"tests.":[66],"Simulations":[67],"on":[68],"a":[69],"Matlab":[70],"model":[71],"loop-backed":[73],"presented":[76],"validate":[78],"feasibility":[80],"method.":[83]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
