{"id":"https://openalex.org/W2094385921","doi":"https://doi.org/10.1145/1119772.1119816","title":"Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL","display_name":"Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2094385921","doi":"https://doi.org/10.1145/1119772.1119816","mag":"2094385921"},"language":"en","primary_location":{"id":"doi:10.1145/1119772.1119816","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119816","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005042451","display_name":"Mohamed-Anouar Dziri","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"M. Anouar Dziri","raw_affiliation_strings":["SLS Group, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"SLS Group, Grenoble, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011011147","display_name":"Firaz Samet","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Firaz Samet","raw_affiliation_strings":["SLS Group, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"SLS Group, Grenoble, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058155284","display_name":"Fl\u00e1vio Rech Wagner","orcid":"https://orcid.org/0000-0003-2199-2785"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Flavio Rech Wagner","raw_affiliation_strings":["UFRGS, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051860238","display_name":"W. Ces\u00e1rio","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wander O. Ces\u00e1rio","raw_affiliation_strings":["SLS Group, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"SLS Group, Grenoble, France","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113780350","display_name":"Ahmed Jerraya","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ahmed A. Jerraya","raw_affiliation_strings":["SLS Group, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"SLS Group, Grenoble, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5005042451"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.484,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.8275991,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"219","last_page":"219"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6994408965110779},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6238386631011963},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6112818121910095},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5695496797561646},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5231010913848877},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.46575361490249634},{"id":"https://openalex.org/keywords/data-flow-analysis","display_name":"Data-flow analysis","score":0.4351979196071625},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4290216863155365},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4136538505554199},{"id":"https://openalex.org/keywords/flow","display_name":"Flow (mathematics)","score":0.4107286036014557},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3547287881374359},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.34585681557655334},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.260878324508667},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.10309827327728271},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07576680183410645}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6994408965110779},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6238386631011963},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6112818121910095},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5695496797561646},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5231010913848877},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.46575361490249634},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.4351979196071625},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4290216863155365},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4136538505554199},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.4107286036014557},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3547287881374359},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.34585681557655334},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.260878324508667},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.10309827327728271},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07576680183410645},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1119772.1119816","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1119772.1119816","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 conference on Asia South Pacific design automation  - ASPDAC","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.15.3028","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.15.3028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ftp://caracol.inf.ufrgs.br/pub/simoo/papers/dziri03.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.387.5852","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.5852","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/03a_1.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323807","display_name":"Institut National Du Cancer","ror":"https://ror.org/03m8vkq32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1495162277","https://openalex.org/W1515109292","https://openalex.org/W2004068104","https://openalex.org/W2037070852","https://openalex.org/W2061341864","https://openalex.org/W2084717429","https://openalex.org/W2100556575","https://openalex.org/W2130163312","https://openalex.org/W2145930857","https://openalex.org/W2152016786","https://openalex.org/W2154317164","https://openalex.org/W2154670520","https://openalex.org/W2172252595","https://openalex.org/W2596660752"],"related_works":["https://openalex.org/W59945861","https://openalex.org/W2388040150","https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W1551967076","https://openalex.org/W2094385921","https://openalex.org/W1528221867","https://openalex.org/W3149244010","https://openalex.org/W2128904268","https://openalex.org/W2047284788"],"abstract_inverted_index":{"Abstract-":[0],"This":[1,30],"paper":[2],"presents":[3],"a":[4,20,51,62,66],"full":[5,21],"System-on-Chip":[6],"(SoC)":[7],"design":[8,27,34,40,48,57,70],"flow":[9],"from":[10],"system":[11,43,55],"specification":[12],"to":[13,18,23],"RT-level.":[14],"A":[15],"new":[16],"approach":[17,31],"obtain":[19],"path":[22],"implementation":[24],"for":[25],"SoC":[26],"is":[28],"proposed.":[29],"combines":[32],"architecture":[33],"space":[35],"exploration":[36],"using":[37,45],"the":[38,46],"VCC":[39],"environment":[41],"and":[42,53],"synthesis":[44],"ROSES":[47],"flow,":[49],"allowing":[50],"true":[52],"complete":[54],"level":[56],"flow.":[58],"The":[59],"experiment":[60],"with":[61],"VDSL":[63],"application":[64],"shows":[65],"significant":[67],"reduction":[68],"of":[69],"time.":[71],"I.":[72]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
