{"id":"https://openalex.org/W2077706339","doi":"https://doi.org/10.1145/1117201.1117258","title":"Building a flexible and scalable DRAM interface for networking applications on FPGAs","display_name":"Building a flexible and scalable DRAM interface for networking applications on FPGAs","publication_year":2006,"publication_date":"2006-02-22","ids":{"openalex":"https://openalex.org/W2077706339","doi":"https://doi.org/10.1145/1117201.1117258","mag":"2077706339"},"language":"en","primary_location":{"id":"doi:10.1145/1117201.1117258","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117258","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110429803","display_name":"Jike Chong","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jike Chong","raw_affiliation_strings":["University of California, Berkeley, Berkeley, CA"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley, Berkeley, CA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041636923","display_name":"Chidamber Kulkarni","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chidamber Kulkarni","raw_affiliation_strings":["Xilinx Inc, San Jose, CA","[Xilinx, Inc., San Jose, CA]"],"affiliations":[{"raw_affiliation_string":"Xilinx Inc, San Jose, CA","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"[Xilinx, Inc., San Jose, CA]","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024404837","display_name":"Gordon Brebner","orcid":"https://orcid.org/0000-0002-9691-459X"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gordon Brebner","raw_affiliation_strings":["Xilinx Inc, San Jose, CA","[Xilinx, Inc., San Jose, CA]"],"affiliations":[{"raw_affiliation_string":"Xilinx Inc, San Jose, CA","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"[Xilinx, Inc., San Jose, CA]","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110429803"],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16464003,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"233","last_page":"233"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.899547278881073},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7963376045227051},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7227743864059448},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.6493729948997498},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6238234043121338},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.602436900138855},{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.599075436592102},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5474260449409485},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5405787825584412},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5276668667793274},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44486716389656067},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.4314594864845276},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.4292525053024292},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.42309510707855225},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4122948944568634},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.33972880244255066},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.31717631220817566},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29028743505477905},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2197447419166565},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2046830952167511},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.19937708973884583},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.12187790870666504},{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.06563764810562134}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.899547278881073},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7963376045227051},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7227743864059448},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.6493729948997498},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6238234043121338},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.602436900138855},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.599075436592102},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5474260449409485},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5405787825584412},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5276668667793274},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44486716389656067},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.4314594864845276},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.4292525053024292},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.42309510707855225},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4122948944568634},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.33972880244255066},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.31717631220817566},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29028743505477905},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2197447419166565},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2046830952167511},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.19937708973884583},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.12187790870666504},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.06563764810562134},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1117201.1117258","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117258","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.108.7042","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.7042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.utah.edu/wmpi/2006/final-version/wmpi-session3-3-Chong.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1981826665","https://openalex.org/W2097215759","https://openalex.org/W2104952512","https://openalex.org/W2115172404","https://openalex.org/W2124584405","https://openalex.org/W2139084641","https://openalex.org/W2145767761"],"related_works":["https://openalex.org/W2555826082","https://openalex.org/W4288804802","https://openalex.org/W4293430534","https://openalex.org/W2335743642","https://openalex.org/W4297812927","https://openalex.org/W2800412005","https://openalex.org/W2172300487","https://openalex.org/W2154976966","https://openalex.org/W2216509856","https://openalex.org/W2624248631"],"abstract_inverted_index":{"A":[0],"fundamental":[1],"challenge":[2,41],"to":[3,38,57,64,96],"successful":[4],"deployment":[5,79],"of":[6,11,26,80,100],"DRAMs":[7],"is":[8,19],"the":[9,22,27,48,78,98],"availability":[10],"a":[12,34,59,74],"flexible":[13,60],"and":[14,51,61,105],"scalable":[15,62],"DRAM":[16,29,72,101],"interface.":[17,30],"This":[18,31],"exacerbated":[20],"by":[21],"application":[23,44],"specific":[24],"nature":[25],"logic-side":[28],"paper":[32],"presents":[33],"study":[35],"that":[36,54,93],"attempts":[37],"overcome":[39],"this":[40,81],"for":[42,70],"networking":[43],"domain.":[45],"We":[46,76,88,108],"quantify":[47],"various":[49],"challenges":[50],"present":[52,89],"techniques":[53,92,111],"were":[55],"implemented":[56],"build":[58],"interface":[63,83],"an":[65],"existing":[66,117],"multi-port":[67],"memory":[68,103,118],"controller":[69],"DDR":[71],"using":[73],"FPGA.":[75],"demonstrate":[77],"new":[82],"in":[84],"two":[85,90],"example":[86],"applications.":[87],"novel":[91],"enable":[94,112],"us":[95],"reduce":[97],"latency":[99],"related":[102],"accesses":[104],"improve":[106],"throughput.":[107],"believe":[109],"our":[110],"harnessing":[113],"maximum":[114],"throughput":[115],"from":[116],"controllers":[119],"with":[120],"least":[121],"possible":[122],"latency.":[123]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
