{"id":"https://openalex.org/W2069693029","doi":"https://doi.org/10.1145/1117201.1117239","title":"A multilevel hierarchical interconnection structure for FPGA","display_name":"A multilevel hierarchical interconnection structure for FPGA","publication_year":2006,"publication_date":"2006-02-22","ids":{"openalex":"https://openalex.org/W2069693029","doi":"https://doi.org/10.1145/1117201.1117239","mag":"2069693029"},"language":"en","primary_location":{"id":"doi:10.1145/1117201.1117239","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117239","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112482028","display_name":"Hayder Mrabet","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Hayder Mrabet","raw_affiliation_strings":["Universit\u00e9 Pierre et Marie Curie, Paris, France"],"affiliations":[{"raw_affiliation_string":"Universit\u00e9 Pierre et Marie Curie, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111822030","display_name":"Zied Marrakchi","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Zied Marrakchi","raw_affiliation_strings":["Universit\u00e9 Pierre et Marie Curie, Paris, France"],"affiliations":[{"raw_affiliation_string":"Universit\u00e9 Pierre et Marie Curie, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004958069","display_name":"Pierre Souillot","orcid":null},"institutions":[{"id":"https://openalex.org/I142476485","display_name":"\u00c9cole Polytechnique","ror":"https://ror.org/05hy3tk52","country_code":"FR","type":"education","lineage":["https://openalex.org/I142476485","https://openalex.org/I4210145102"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Pierre Souillot","raw_affiliation_strings":["Ecole Polytechnique, France","Ecole polytechnique, France#TAB#"],"affiliations":[{"raw_affiliation_string":"Ecole Polytechnique, France","institution_ids":["https://openalex.org/I142476485"]},{"raw_affiliation_string":"Ecole polytechnique, France#TAB#","institution_ids":["https://openalex.org/I142476485"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108405631","display_name":"Habib Mehrez","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Habib Mehrez","raw_affiliation_strings":["Universit\u00e9 Pierre et Marie Curie, Paris, France"],"affiliations":[{"raw_affiliation_string":"Universit\u00e9 Pierre et Marie Curie, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5112482028"],"corresponding_institution_ids":["https://openalex.org/I39804081"],"apc_list":null,"apc_paid":null,"fwci":0.7637,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.74339102,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"225","last_page":"225"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7062590718269348},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5896642208099365},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5628852844238281},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5132269859313965},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.512950599193573},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4925461709499359},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4900878667831421},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4871227741241455},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.4589790403842926},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4572458267211914},{"id":"https://openalex.org/keywords/network-architecture","display_name":"Network architecture","score":0.44417744874954224},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4329034686088562},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39495640993118286},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.38917243480682373},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3702165186405182},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.33011215925216675},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15349650382995605},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09178745746612549}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7062590718269348},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5896642208099365},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5628852844238281},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5132269859313965},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.512950599193573},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4925461709499359},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4900878667831421},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4871227741241455},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.4589790403842926},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4572458267211914},{"id":"https://openalex.org/C193415008","wikidata":"https://www.wikidata.org/wiki/Q639681","display_name":"Network architecture","level":2,"score":0.44417744874954224},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4329034686088562},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39495640993118286},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.38917243480682373},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3702165186405182},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.33011215925216675},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15349650382995605},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09178745746612549},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1117201.1117239","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117239","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-01338215v1","is_oa":false,"landing_page_url":"https://hal.science/hal-01338215","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. pp.225-225, ⟨10.1145/1117201.1117239⟩","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2089341644","https://openalex.org/W1490954251","https://openalex.org/W2126255765","https://openalex.org/W2121539644","https://openalex.org/W2993587745","https://openalex.org/W218334444","https://openalex.org/W2794977832","https://openalex.org/W2057027737","https://openalex.org/W2308099738","https://openalex.org/W2765531298"],"abstract_inverted_index":{"Creation":[0],"of":[1,71,164],"large":[2],"FPGAs":[3],"needs":[4],"radical":[5],"efficient":[6],"changes":[7],"in":[8,136,144,180,186],"architecture":[9,51,204],"to":[10,82,139,160,194,219],"improve":[11],"speed,":[12],"density":[13],"and":[14,29,37,55,91,112,125,129,156,177,198,205,215,238],"software":[15,38,211],"mapping":[16],"time.":[17],"Based":[18],"on":[19,77,108,170,223],"industry":[20],"experience":[21],"with":[22,235],"standard":[23],"ASICs,":[24],"we":[25,43,75],"believe":[26],"that":[27,116,175,230],"partitioning":[28],"hierarchy":[30],"become":[31],"an":[32,41,113],"obligation":[33],"for":[34,213],"FPGA":[35,49,73],"hardware":[36],"developments.":[39],"As":[40],"alternative":[42],"propose":[44],"a":[45,239],"new":[46],"Multilevel":[47],"hierarchical":[48],"(MFPGA)":[50],"where":[52],"logic":[53,92,153],"blocks":[54,154],"routing":[56,67,216],"resources":[57,68],"are":[58],"sparsely":[59],"partitioned":[60],"into":[61],"multilevel":[62],"clustered":[63],"structure.":[64],"Since":[65],"the":[66,72,84,109,137,145,152,157,161,165,171,181,196,206,224],"consume":[69],"most":[70],"area,":[74],"focus":[76],"interconnect":[78,90,98],"check.":[79],"We":[80,189],"try":[81],"achieve":[83],"best":[85],"area":[86,199,242],"efficiency":[87],"by":[88],"balancing":[89],"block":[93],"utilization.":[94],"The":[95,119,148],"proposed":[96],"MFPGA":[97,182,203,225,231],"unifies":[99],"two":[100],"unidirectional":[101,126],"programmable":[102],"networks:":[103],"A":[104],"downward":[105,166],"network":[106,115,121,150],"based":[107,169],"Butterfly-Fat-Tree":[110],"topology,":[111],"upward":[114,149],"uses":[117,122],"hierarchy.":[118],"Downward":[120],"linear":[123],"populated":[124],"switch":[127,178,197],"boxes":[128],"gives":[130],"one":[131],"path":[132],"from":[133],"each":[134,140],"wire-source":[135],"top":[138],"leaf":[141],"(logic":[142],"block)":[143],"lowest":[146],"level.":[147],"connects":[151],"outputs":[155],"input":[158],"pads":[159],"different":[162],"levels":[163],"network.":[167],"Studies":[168],"Rent's":[172],"Rule":[173],"show":[174,229],"wiring":[176],"requirements":[179,200],"grow":[183],"slower":[184],"than":[185,243],"traditional":[187,207],"topologies.":[188],"used":[190],"MCNC":[191],"benchmark":[192],"circuits":[193,234],"compare":[195],"between":[201],"our":[202],"mesh":[208,244],"topology.":[209],"New":[210],"tools":[212],"placement":[214],"were":[217],"developed":[218],"conduct":[220],"this":[221],"study":[222],"architecture.":[226,245],"Expermimental":[227],"results":[228],"can":[232],"implement":[233],"fewer":[236],"switches":[237],"smaller":[240],"total":[241]},"counts_by_year":[],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}