{"id":"https://openalex.org/W2079562273","doi":"https://doi.org/10.1145/1117201.1117234","title":"FPGAs with multidimensional mesh topology","display_name":"FPGAs with multidimensional mesh topology","publication_year":2006,"publication_date":"2006-02-22","ids":{"openalex":"https://openalex.org/W2079562273","doi":"https://doi.org/10.1145/1117201.1117234","mag":"2079562273"},"language":"en","primary_location":{"id":"doi:10.1145/1117201.1117234","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117234","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110465575","display_name":"Yohei Matsumoto","orcid":null},"institutions":[{"id":"https://openalex.org/I73613424","display_name":"National Institute of Advanced Industrial Science and Technology","ror":"https://ror.org/01703db54","country_code":"JP","type":"government","lineage":["https://openalex.org/I73613424"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Yohei Matsumoto","raw_affiliation_strings":["National Institution of Advanced Industrial Science and Technology, Tsukuba-shi, Japan"],"affiliations":[{"raw_affiliation_string":"National Institution of Advanced Industrial Science and Technology, Tsukuba-shi, Japan","institution_ids":["https://openalex.org/I73613424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112437600","display_name":"Hanpei Koike","orcid":null},"institutions":[{"id":"https://openalex.org/I73613424","display_name":"National Institute of Advanced Industrial Science and Technology","ror":"https://ror.org/01703db54","country_code":"JP","type":"government","lineage":["https://openalex.org/I73613424"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hanpei Koike","raw_affiliation_strings":["National Institution of Advanced Industrial Science and Technology, Tsukuba-shi, Japan"],"affiliations":[{"raw_affiliation_string":"National Institution of Advanced Industrial Science and Technology, Tsukuba-shi, Japan","institution_ids":["https://openalex.org/I73613424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001577851","display_name":"A. Masaki","orcid":null},"institutions":[{"id":"https://openalex.org/I163770644","display_name":"Okayama University","ror":"https://ror.org/02pc6pc55","country_code":"JP","type":"education","lineage":["https://openalex.org/I163770644"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akira Masaki","raw_affiliation_strings":["Okayama University, Okayama-shi, Japan"],"affiliations":[{"raw_affiliation_string":"Okayama University, Okayama-shi, Japan","institution_ids":["https://openalex.org/I163770644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110465575"],"corresponding_institution_ids":["https://openalex.org/I73613424"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16309118,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"223","last_page":"223"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8673087954521179},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.6353287100791931},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6180069446563721},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5711283087730408},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5394929051399231},{"id":"https://openalex.org/keywords/embedding","display_name":"Embedding","score":0.5320117473602295},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5244184732437134},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4613751173019409},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2743384838104248},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.25038599967956543},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07228314876556396},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07039308547973633}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8673087954521179},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.6353287100791931},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6180069446563721},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5711283087730408},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5394929051399231},{"id":"https://openalex.org/C41608201","wikidata":"https://www.wikidata.org/wiki/Q980509","display_name":"Embedding","level":2,"score":0.5320117473602295},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5244184732437134},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4613751173019409},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2743384838104248},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.25038599967956543},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07228314876556396},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07039308547973633},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1117201.1117234","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117234","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3146360095","https://openalex.org/W2184011203","https://openalex.org/W4399458808","https://openalex.org/W2367348190","https://openalex.org/W594316872","https://openalex.org/W2831860248","https://openalex.org/W2367794224","https://openalex.org/W2072850836","https://openalex.org/W1968650434","https://openalex.org/W2105610663"],"abstract_inverted_index":{"In":[0],"a":[1,24,35,46,65,83,88,92,109,114,121,139,151,159,169,174],"traditional":[2,97],"2-D":[3,98,110,122,160,175],"field-programmable":[4],"gate":[5,51],"array":[6],"(FPGA),":[7],"the":[8,15,27,56,70,96,129,142,165],"number":[9,16,48,58],"of":[10,17,59,82,95,131,144,168,184],"routing":[11],"switches":[12],"increases":[13],"as":[14,91],"logic":[18,28],"gates":[19],"increases,":[20],"and":[21,43,99,102,182,190],"thereby":[22],"causes":[23,138],"decrease":[25],"in":[26,128,147],"density.":[29],"DeHon":[30],"et":[31],"al.":[32],"demonstrated":[33],"that":[34,64,68,81,164],"tree-based":[36,84],"FPGA":[37,67,90,116,153,171,176],"they":[38],"proposed":[39],"resolves":[40],"this":[41],"problem":[42],"requires":[44],"only":[45],"constant":[47],"ofswitches":[49],"per":[50],"without":[52],"any":[53],"relation":[54],"to":[55,80],"total":[57],"gates.":[60],"This":[61],"paper":[62],"presents":[63],"multidimensional":[66,71,89,115,152],"exploits":[69],"mesh":[72],"topology":[73],"also":[74],"achieves":[75],"asymptotically":[76],"identical":[77],"area":[78],"efficiency":[79],"FPGA.":[85,161],"We":[86,112,162],"model":[87],"simple":[93],"extension":[94],"3-D":[100],"FPGAs,":[101],"realize":[103],"it":[104,107],"by":[105,187],"embedding":[106,136],"onto":[108,120],"chip.":[111],"show":[113,163],"can":[117],"be":[118],"embedded":[119],"chip":[123],"with":[124,173,179],"no":[125],"critical":[126],"increase":[127],"amount":[130],"metal":[132],"wiring.":[133],"Although":[134],"our":[135],"method":[137],"gap":[140],"between":[141],"lengths":[143],"wire":[145],"segments":[146],"different":[148],"axial":[149],"directions,":[150],"indicates":[154],"lower":[155],"interconnection":[156],"delay":[157],"than":[158],"speed":[166],"advantage":[167],"4-D":[170],"compared":[172],"extends":[177],"along":[178],"further":[180],"integration":[181],"scaling":[183],"semiconductor":[185],"devices":[186],"predicting":[188],"maximum":[189],"average":[191],"net":[192],"delays.":[193]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
