{"id":"https://openalex.org/W2033685698","doi":"https://doi.org/10.1145/1117201.1117216","title":"FPGA clock network architecture","display_name":"FPGA clock network architecture","publication_year":2006,"publication_date":"2006-02-22","ids":{"openalex":"https://openalex.org/W2033685698","doi":"https://doi.org/10.1145/1117201.1117216","mag":"2033685698"},"language":"en","primary_location":{"id":"doi:10.1145/1117201.1117216","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117216","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074883642","display_name":"Julien Lamoureux","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Julien Lamoureux","raw_affiliation_strings":["University of British Columbia, Vancouver, B.C., Canada"],"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, B.C., Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J. E. Wilton","raw_affiliation_strings":["University of British Columbia, Vancouver, B.C., Canada"],"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, B.C., Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074883642"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":5.3612,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.95487218,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"101","last_page":"108"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.8240368366241455},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6951197981834412},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6384738683700562},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6332095861434937},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6220309138298035},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5951251983642578},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.563077449798584},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5295121669769287},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.41443219780921936},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3962938189506531},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.3887709975242615},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.2900581955909729},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.24016636610031128},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07480421662330627}],"concepts":[{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.8240368366241455},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6951197981834412},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6384738683700562},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6332095861434937},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6220309138298035},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5951251983642578},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.563077449798584},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5295121669769287},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.41443219780921936},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3962938189506531},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.3887709975242615},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.2900581955909729},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.24016636610031128},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07480421662330627},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1117201.1117216","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117216","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1502531259","https://openalex.org/W1523051745","https://openalex.org/W1574542534","https://openalex.org/W2007362516","https://openalex.org/W2016748970","https://openalex.org/W2024701939","https://openalex.org/W2095558812","https://openalex.org/W2097521167"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W2474747038","https://openalex.org/W3006003651","https://openalex.org/W4313332229","https://openalex.org/W2137310043","https://openalex.org/W2803012234"],"abstract_inverted_index":{"This":[0],"paper":[1,21],"examines":[2],"the":[3,41,61,65,67,72,75,82,97,113],"tradeoffs":[4],"between":[5],"flexibility,":[6],"area,":[7],"and":[8,48,52,91,102,129],"power":[9,92,103],"dissipation":[10],"of":[11,35,55,60,74,84,89],"programmable":[12,36],"clock":[13,27,37,50,62,76,120,124,135,139],"networks":[14,108,121,136],"for":[15,107,141],"Field-Programmable":[16],"Gate":[17],"Arrays":[18],"(FPGA's).":[19],"The":[20],"begins":[22],"by":[23],"describing":[24],"a":[25,32],"parameterized":[26],"network":[28,38,77],"model":[29,42],"that":[30,70,100,119],"describes":[31],"broad":[33],"range":[34],"architectures.":[39],"Specifically,":[40],"supports":[43],"architectures":[44],"with":[45,109,122,143],"multiple":[46,144],"local":[47,123,138],"global":[49],"domains":[51,125,140],"varying":[53],"amounts":[54],"flexibility":[56,73,86,110],"at":[57],"various":[58],"levels":[59],"network.":[63],"Using":[64],"model,":[66],"architectural":[68],"parameters":[69],"control":[71],"are":[78,105,130],"varied":[79],"to":[80,112],"determine":[81],"cost":[83],"this":[85],"in":[87],"terms":[88],"area":[90,101],"dissipation.":[93],"From":[94],"these":[95],"experiments,":[96],"study":[98],"finds":[99],"costs":[104],"highest":[106],"close":[111],"logic":[114],"blocks.":[115],"Furthermore,":[116],"it":[117],"found":[118],"have":[126],"little":[127],"overhead":[128],"significantly":[131],"more":[132],"efficient":[133],"than":[134],"without":[137],"applications":[142],"clocks.":[145]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
