{"id":"https://openalex.org/W1971491113","doi":"https://doi.org/10.1145/1117201.1117211","title":"Design, implementation, and verification of active cache emulator (ACE)","display_name":"Design, implementation, and verification of active cache emulator (ACE)","publication_year":2006,"publication_date":"2006-02-22","ids":{"openalex":"https://openalex.org/W1971491113","doi":"https://doi.org/10.1145/1117201.1117211","mag":"1971491113"},"language":"en","primary_location":{"id":"doi:10.1145/1117201.1117211","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014078681","display_name":"Jumnit Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jumnit Hong","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Intel Corporation, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084078152","display_name":"Eriko Nurvitadhi","orcid":"https://orcid.org/0000-0002-2347-9590"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eriko Nurvitadhi","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA","Carnegie-Mellon University, Pittsburgh, PA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie-Mellon University, Pittsburgh, PA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113526607","display_name":"Shih\u2010Lien L. Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shih-Lien L. Lu","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Intel Corporation, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5014078681"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":2.558,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.88830058,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"63","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8217374086380005},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.765555739402771},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6354584097862244},{"id":"https://openalex.org/keywords/pentium","display_name":"Pentium","score":0.6333376169204712},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.5645139813423157},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.5294023752212524},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.5194977521896362},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.4727792739868164},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.42531150579452515},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.41064178943634033},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.41063350439071655},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.41059380769729614},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.385474294424057},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3409423530101776}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8217374086380005},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.765555739402771},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6354584097862244},{"id":"https://openalex.org/C46268123","wikidata":"https://www.wikidata.org/wiki/Q214314","display_name":"Pentium","level":2,"score":0.6333376169204712},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.5645139813423157},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.5294023752212524},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.5194977521896362},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.4727792739868164},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.42531150579452515},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.41064178943634033},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.41063350439071655},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.41059380769729614},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.385474294424057},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3409423530101776},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1117201.1117211","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.84.4012","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.84.4012","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.cmu.edu/~enurvita/docs/ace-fpga2006-final.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1495659829","https://openalex.org/W1496583045","https://openalex.org/W1595118008","https://openalex.org/W1975079715","https://openalex.org/W1990397567","https://openalex.org/W2020235248","https://openalex.org/W2117958469","https://openalex.org/W2136321560","https://openalex.org/W2153456949","https://openalex.org/W4232134245"],"related_works":["https://openalex.org/W2903846315","https://openalex.org/W4312759433","https://openalex.org/W2290179447","https://openalex.org/W1994369542","https://openalex.org/W2123859627","https://openalex.org/W2102697714","https://openalex.org/W2793052975","https://openalex.org/W2161101294","https://openalex.org/W2057019356","https://openalex.org/W2086718556"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,9,36,67,70,74,83,92,99,117,147,152,158,173,185,198,202],"design,":[4],"implementation,":[5],"and":[6,24,188,205],"verification":[7],"of":[8,69,91,101,134,151,181,197],"Active":[10],"Cache":[11,186],"Emulator":[12],"(ACE),":[13],"a":[14,130,135,166],"novel":[15],"FPGA-based":[16,47],"emulator":[17],"that":[18,50],"models":[19],"an":[20],"L3":[21],"cache":[22,48,72,143,200],"actively":[23,141],"in":[25,113],"real-time.":[26],"ACE":[27,59,145,162,182,207],"leverages":[28],"interactions":[29],"with":[30,129,209],"its":[31,63,177],"host":[32,57,64,84,203],"system":[33,38,41,85],"to":[34,62,80,115,127,154,157,193],"model":[35],"target":[37],"(i.e.":[39],"hypothetical":[40],"under":[42],"study).":[43],"Unlike":[44],"most":[45],"existing":[46],"emulators":[49],"collect":[51],"only":[52],"memory":[53],"traces":[54],"from":[55],"their":[56],"system,":[58,204],"provides":[60],"feedback":[61],"by":[65,104,201],"modeling":[66],"impact":[68],"emulated":[71,93,199],"on":[73],"system.":[75,139,159],"Specifically,":[76],"delays":[77,156],"are":[78],"injected":[79],"time":[81],"dilate":[82],"which":[86],"then":[87],"experiences":[88],"hit/miss":[89],"latencies":[90],"cache.":[94],"Such":[95],"active":[96],"emulation":[97],"expands":[98],"context":[100],"performance":[102,107,120],"measurements":[103],"capturing":[105],"processor":[106],"metrics":[108,121],"(e.g.":[109,122],"cycle":[110],"per":[111],"instruction)":[112],"addition":[114],"measuring":[116],"typical":[118,136],"cache-specific":[119],"miss":[123],"ratio).ACE":[124],"is":[125,163],"designed":[126],"interface":[128],"front-side":[131],"bus":[132],"(FSB)":[133],"Pentium\u00ae-based":[137],"PC":[138],"To":[140],"emulate":[142],"latencies,":[144],"utilizes":[146],"snoop":[148],"stall":[149],"mechanism":[150],"FSB":[153],"inject":[155],"At":[160],"present,":[161],"implemented":[164],"using":[165,184],"Xilinx":[167],"XC2V6000":[168],"FPGA":[169],"running":[170],"at":[171],"66MHz,":[172],"same":[174],"speed":[175],"as":[176],"host's":[178],"FSB.":[179],"Verification":[180],"includes":[183],"Calibrator":[187],"RightMark":[189],"Memory":[190],"Analyzer":[191],"software":[192,211],"confirm":[194],"proper":[195],"detection":[196],"comparing":[206],"results":[208],"SimpleScalar":[210],"simulations.":[212]},"counts_by_year":[{"year":2014,"cited_by_count":2}],"updated_date":"2026-04-28T14:05:53.105641","created_date":"2025-10-10T00:00:00"}
