{"id":"https://openalex.org/W2168261632","doi":"https://doi.org/10.1145/1117201.1117207","title":"Optimality study of logic synthesis for LUT-based FPGAs","display_name":"Optimality study of logic synthesis for LUT-based FPGAs","publication_year":2006,"publication_date":"2006-02-22","ids":{"openalex":"https://openalex.org/W2168261632","doi":"https://doi.org/10.1145/1117201.1117207","mag":"2168261632"},"language":"en","primary_location":{"id":"doi:10.1145/1117201.1117207","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117207","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102170602","display_name":"Jason Cong","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jason Cong","raw_affiliation_strings":["University of California, Los Angeles, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035560173","display_name":"Kirill Minkovich","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kirill Minkovich","raw_affiliation_strings":["University of California, Los Angeles, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5102170602"],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":3.8305,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.93419017,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"33","last_page":"40"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.806159496307373},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.7082158923149109},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6688084602355957},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.615371823310852},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.6084120869636536},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.51576828956604},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4546826183795929},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45416077971458435},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.452282190322876},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4384566843509674},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3964485228061676},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37092721462249756},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3560304641723633},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2278803586959839},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07147866487503052}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.806159496307373},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.7082158923149109},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6688084602355957},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.615371823310852},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.6084120869636536},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.51576828956604},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4546826183795929},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45416077971458435},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.452282190322876},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4384566843509674},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3964485228061676},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37092721462249756},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3560304641723633},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2278803586959839},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07147866487503052}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1117201.1117207","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117207","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.75.8049","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.75.8049","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cadlab.cs.ucla.edu/~cong/papers/fp81-minkovich-v2.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.86.4577","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.86.4577","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cadlab.cs.ucla.edu/~kirill/fpga06.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6000000238418579,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W3381706","https://openalex.org/W1511688816","https://openalex.org/W1556439630","https://openalex.org/W1905608265","https://openalex.org/W1970296212","https://openalex.org/W1971436411","https://openalex.org/W1978998136","https://openalex.org/W1985457698","https://openalex.org/W1989931041","https://openalex.org/W1996746141","https://openalex.org/W2011039300","https://openalex.org/W2016990398","https://openalex.org/W2052067881","https://openalex.org/W2069508824","https://openalex.org/W2072740520","https://openalex.org/W2082998942","https://openalex.org/W2101952163","https://openalex.org/W2105715355","https://openalex.org/W2106290133","https://openalex.org/W2108914609","https://openalex.org/W2119248453","https://openalex.org/W2120970098","https://openalex.org/W2134060873","https://openalex.org/W2136569261","https://openalex.org/W2137806747","https://openalex.org/W2147345706","https://openalex.org/W2150787480","https://openalex.org/W2155626237","https://openalex.org/W2160671668","https://openalex.org/W2163632212","https://openalex.org/W2167328871","https://openalex.org/W2171775842","https://openalex.org/W2173471405","https://openalex.org/W2175238470","https://openalex.org/W2244550955","https://openalex.org/W3217272585","https://openalex.org/W4248181708"],"related_works":["https://openalex.org/W3011978806","https://openalex.org/W3204573923","https://openalex.org/W3207169898","https://openalex.org/W3198354237","https://openalex.org/W2743305891","https://openalex.org/W4385309418","https://openalex.org/W2331259470","https://openalex.org/W2019954703","https://openalex.org/W4379115868","https://openalex.org/W2157128002"],"abstract_inverted_index":{"FPGA":[0,45,60,133,164,206],"logic":[1,38,78,148],"synthesis":[2,39,149,165],"and":[3,40,80,120,125,162,178,203],"technology":[4,41,81,115,134],"mapping":[5,42,82,135],"have":[6,110],"been":[7],"studied":[8],"extensively":[9],"over":[10],"the":[11,18,36,73,143,146],"past":[12],"15":[13],"years.":[14],"However,":[15],"progress":[16],"within":[17],"last":[19],"few":[20],"years":[21],"has":[22],"slowed":[23],"considerably":[24],"(with":[25],"some":[26,180],"notable":[27],"exceptions).":[28],"It":[29],"seems":[30],"natural":[31],"to":[32,93,140],"then":[33],"question":[34],"whether":[35],"current":[37],"algorithms":[43,70,136],"for":[44,104,200],"designs":[46],"are":[47,53,71,84,155,167],"producing":[48],"near-optimal":[49],"solutions.":[50],"Although":[51],"there":[52,196],"many":[54],"empirical":[55],"studies":[56],"that":[57,76,109,130,195],"compare":[58],"different":[59],"synthesis/mapping":[61],"algorithms,":[62],"little":[63],"is":[64,197],"known":[65,111],"about":[66],"how":[67],"far":[68,156],"these":[69,118],"from":[72,145,157],"optimal":[74,112,141],"(recall":[75],"both":[77],"optimization":[79,90,152],"problems":[83],"NP-hard":[85],"if":[86],"we":[87,99,128],"consider":[88],"area":[89,175],"in":[91,172,179,205],"addition":[92],"delay/depth":[94],"optimization).":[95],"In":[96],"this":[97],"paper":[98],"present":[100],"a":[101],"novel":[102],"method":[103],"constructing":[105],"arbitrarily":[106],"large":[107],"circuits":[108,119],"solutions":[113],"after":[114],"mapping.":[116],"Using":[117],"their":[121],"derivatives":[122],"(called":[123],"LEKO":[124],"LEKU,":[126],"respectively),":[127],"show":[129],"although":[131],"leading":[132],"can":[137],"produce":[138],"close":[139],"solutions,":[142],"results":[144,192],"entire":[147],"flow":[150],"(logic":[151],"+":[153],"mapping)":[154],"optimal.":[158],"The":[159],"best":[160],"industrial":[161],"academic":[163],"flows":[166],"around":[168],"140":[169],"times":[170,186],"larger":[171,187],"terms":[173],"of":[174],"on":[176,188],"average,":[177],"cases":[181],"as":[182,184],"much":[183,198],"500":[185],"LEKU":[189],"examples.":[190],"These":[191],"clearly":[193],"indicate":[194],"room":[199],"further":[201],"research":[202],"improvement":[204],"synthesis.":[207]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-18T07:56:08.524223","created_date":"2025-10-10T00:00:00"}