{"id":"https://openalex.org/W2169510913","doi":"https://doi.org/10.1145/1084834.1084894","title":"SOMA","display_name":"SOMA","publication_year":2005,"publication_date":"2005-09-19","ids":{"openalex":"https://openalex.org/W2169510913","doi":"https://doi.org/10.1145/1084834.1084894","mag":"2169510913"},"language":"en","primary_location":{"id":"doi:10.1145/1084834.1084894","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1084834.1084894","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035738831","display_name":"Girish Venkataramani","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Girish Venkataramani","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026892801","display_name":"Tiberiu Chelcea","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tiberiu Chelcea","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056068651","display_name":"Seth Copen Goldstein","orcid":"https://orcid.org/0000-0003-1512-0446"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Seth Copen Goldstein","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066739996","display_name":"T. Bjerregaard","orcid":null},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Tobias Bjerregaard","raw_affiliation_strings":["TU Denmark, Lyngby, Denmark"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TU Denmark, Lyngby, Denmark","institution_ids":["https://openalex.org/I96673099"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5035738831"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":1.8474,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.86604843,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"231","last_page":"236"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8509144186973572},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.576210618019104},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5428495407104492},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5085984468460083},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45898497104644775},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.43663516640663147},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38897451758384705},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3508830666542053},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.33869415521621704},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2555050849914551},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.18591314554214478}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8509144186973572},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.576210618019104},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5428495407104492},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5085984468460083},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45898497104644775},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.43663516640663147},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38897451758384705},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3508830666542053},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.33869415521621704},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2555050849914551},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.18591314554214478},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1084834.1084894","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1084834.1084894","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1578265651","https://openalex.org/W1969982904","https://openalex.org/W1986342413","https://openalex.org/W2004094800","https://openalex.org/W2017785995","https://openalex.org/W2017906722","https://openalex.org/W2031172980","https://openalex.org/W2065719575","https://openalex.org/W2065933945","https://openalex.org/W2087612811","https://openalex.org/W2097048259","https://openalex.org/W2098996548","https://openalex.org/W2106755614","https://openalex.org/W2115488561","https://openalex.org/W2117285153","https://openalex.org/W2120961842","https://openalex.org/W2139904769","https://openalex.org/W2145494916","https://openalex.org/W2147832021","https://openalex.org/W2153179875","https://openalex.org/W2158600037","https://openalex.org/W2159357353","https://openalex.org/W2159910937","https://openalex.org/W2161520589","https://openalex.org/W2169736898","https://openalex.org/W2296054660","https://openalex.org/W2914074464","https://openalex.org/W4231905827","https://openalex.org/W6674565536"],"related_works":["https://openalex.org/W3108003711","https://openalex.org/W254684032","https://openalex.org/W120214571","https://openalex.org/W2036525499","https://openalex.org/W2334181344","https://openalex.org/W207100770","https://openalex.org/W1848192231","https://openalex.org/W2546116848","https://openalex.org/W2043352873","https://openalex.org/W2934889147"],"abstract_inverted_index":{"Arbitrary":[0],"memory":[1,6,38,45,63,80],"dependencies":[2],"and":[3,159],"variable":[4],"latency":[5],"systems":[7,17],"are":[8],"major":[9],"obstacles":[10],"to":[11,60,76,90],"the":[12,41,78,84,92,97,100],"synthesis":[13,26,137],"of":[14,43,83,124],"large-scale":[15],"ASIC":[16],"in":[18,40,51],"high-level":[19],"synthesis.":[20],"This":[21,86],"paper":[22],"presents":[23],"SOMA,":[24],"a":[25,61,121],"framework":[27],"for":[28,105],"constructing":[29],"Memory":[30],"Access":[31],"Network":[32],"(MAN)":[33],"architectures":[34],"that":[35,151],"inherently":[36],"enforce":[37],"consistency":[39],"presence":[42],"dynamic":[44,79],"access":[46],"dependencies.":[47],"A":[48],"fundamental":[49],"bottleneck":[50],"any":[52],"such":[53],"network":[54,125],"is":[55,87,113],"arbitrating":[56],"between":[57],"concurrent":[58],"accesses":[59],"shared":[62],"resource.":[64],"To":[65],"alleviate":[66],"this":[67],"bottleneck,":[68],"SOMA":[69,128],"uses":[70],"an":[71,134],"application-specific":[72],"concurrency":[73],"analysis":[74],"technique":[75],"predict":[77],"parallelism":[81,98],"profile":[82],"application.":[85],"then":[88],"used":[89],"customize":[91],"MAN":[93,101,112,154],"architecture.":[94],"Depending":[95],"on":[96],"profile,":[99],"may":[102],"be":[103],"optimized":[104,111],"latency,":[106],"throughput":[107],"or":[108],"both.":[109],"The":[110],"automatically":[114],"synthesized":[115],"into":[116,133],"gate-level":[117],"structural":[118],"Verilog":[119],"using":[120],"flexible":[122],"library":[123],"building":[126],"blocks.":[127],"has":[129],"been":[130],"successfully":[131],"integrated":[132],"automated":[135],"C-to-hardware":[136],"flow,":[138],"which":[139],"generates":[140],"standard":[141],"cell":[142],"circuits":[143],"from":[144],"unrestricted":[145],"ANSI-C":[146],"programs.":[147],"Post-layout":[148],"experiments":[149],"demonstrate":[150],"application":[152],"specific":[153],"construction":[155],"significantly":[156],"improves":[157],"power":[158],"performance.":[160]},"counts_by_year":[],"updated_date":"2026-04-28T14:05:53.105641","created_date":"2016-06-24T00:00:00"}