{"id":"https://openalex.org/W2007698668","doi":"https://doi.org/10.1145/1081081.1081126","title":"Design of a radix-2<sup>m</sup> hybrid array multiplier using carry save adder format","display_name":"Design of a radix-2<sup>m</sup> hybrid array multiplier using carry save adder format","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2007698668","doi":"https://doi.org/10.1145/1081081.1081126","mag":"2007698668"},"language":"en","primary_location":{"id":"doi:10.1145/1081081.1081126","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1081081.1081126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual symposium on Integrated circuits and system design  - SBCCI '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068978110","display_name":"Mateus Beck Fonseca","orcid":null},"institutions":[{"id":"https://openalex.org/I110676245","display_name":"Universidade Cat\u00f3lica de Pelotas","ror":"https://ror.org/0376myh60","country_code":"BR","type":"education","lineage":["https://openalex.org/I110676245"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"M. Fonseca","raw_affiliation_strings":["Universidade Cat\u00edlica de Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Cat\u00edlica de Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I110676245"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074598853","display_name":"Eduardo Costa","orcid":"https://orcid.org/0009-0009-2731-8864"},"institutions":[{"id":"https://openalex.org/I110676245","display_name":"Universidade Cat\u00f3lica de Pelotas","ror":"https://ror.org/0376myh60","country_code":"BR","type":"education","lineage":["https://openalex.org/I110676245"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"E. da Costa","raw_affiliation_strings":["Universidade Cat\u00edlica de Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Cat\u00edlica de Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I110676245"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046426137","display_name":"S\u00e9rgio Bampi","orcid":"https://orcid.org/0000-0002-9018-6309"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"S. Bampi","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039448613","display_name":"Jos\u00e9 Monteiro","orcid":"https://orcid.org/0000-0003-0603-2268"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J. Monteiro","raw_affiliation_strings":["IST/INESC-ID, Lisbon, Portugal","IST / INESC-ID Lisbon, Portugal"],"affiliations":[{"raw_affiliation_string":"IST/INESC-ID, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"IST / INESC-ID Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5068978110"],"corresponding_institution_ids":["https://openalex.org/I110676245"],"apc_list":null,"apc_paid":null,"fwci":0.3557,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.63771748,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"172","last_page":"172"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8726217746734619},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.7806017398834229},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.6603687405586243},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5564186573028564},{"id":"https://openalex.org/keywords/booths-multiplication-algorithm","display_name":"Booth's multiplication algorithm","score":0.492241770029068},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.4352811574935913},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.4320067763328552},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39526230096817017},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.39230889081954956},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3893055021762848},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33317282795906067},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3208208680152893},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.28567564487457275},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15084105730056763},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12259754538536072},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.09986093640327454}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8726217746734619},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7806017398834229},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.6603687405586243},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5564186573028564},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.492241770029068},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.4352811574935913},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.4320067763328552},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39526230096817017},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.39230889081954956},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3893055021762848},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33317282795906067},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3208208680152893},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.28567564487457275},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15084105730056763},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12259754538536072},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.09986093640327454},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1081081.1081126","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1081081.1081126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual symposium on Integrated circuits and system design  - SBCCI '05","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W165339164","https://openalex.org/W1974361683","https://openalex.org/W1983849809","https://openalex.org/W2117442011","https://openalex.org/W2117453169","https://openalex.org/W2120630202","https://openalex.org/W2124063495","https://openalex.org/W2143797077","https://openalex.org/W2154098113","https://openalex.org/W2168350974"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W2953746839","https://openalex.org/W2370097872","https://openalex.org/W2112595260","https://openalex.org/W4295540194","https://openalex.org/W986131379","https://openalex.org/W1993041309"],"abstract_inverted_index":{"In":[0,54,94],"this":[1,61,95],"work,":[2],"we":[3,57,73,97,113],"present":[4,58,74],"a":[5,8,65],"design":[6],"of":[7,151,165],"radix-2m":[9],"Hybrid":[10,35,78,101,127],"array":[11],"multiplier":[12,36,62,102,128],"using":[13,44,64,109,119,157],"Carry":[14,46],"Save":[15],"Adder":[16],"(CSA)":[17],"circuit":[18],"in":[19,24,41,49,60,84,121,149],"the":[20,28,32,42,50,69,77,90,100,104,122,126,134,147,166],"partial":[21,51,123],"product":[22,52,124],"lines":[23],"order":[25],"to":[26,141],"speed-up":[27],"carry":[29],"propagation":[30],"along":[31,68],"array.":[33],"The":[34,71,111],"architecture":[37,79,91],"was":[38],"previously":[39],"presented":[40],"literature":[43],"Ripple":[45],"Adders":[47],"(RCA)":[48],"lines.":[53],"our":[55],"work":[56,96],"improvements":[59],"by":[63,156],"faster":[66],"CSA":[67,81,120],"circuit.":[70,137],"results":[72,112],"show":[75,116],"that":[76,117],"with":[80,89,92],"compares":[82],"favorably":[83],"area,":[85,152],"performance":[86],"and":[87,154,163],"power":[88,155],"RCA.":[93],"also":[98],"compare":[99,146],"against":[103],"Modified":[105,135],"Booth":[106,136],"multiplier,":[107],"both":[108],"CSA.":[110],"have":[114],"obtained":[115],"after":[118],"lines,":[125],"is":[129],"significantly":[130],"more":[131],"efficient":[132],"than":[133],"Power":[138],"savings":[139],"close":[140],"25%":[142],"are":[143,168],"achievable.":[144],"We":[145],"multipliers":[148,167],"terms":[150],"delay":[153],"Altera":[158,171],"Quartus":[159],"II":[160],"tool.":[161],"Synthesis":[162],"simulation":[164],"performed":[169],"for":[170],"Stratix":[172],"device.":[173]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}