{"id":"https://openalex.org/W2151467224","doi":"https://doi.org/10.1145/1077603.1077630","title":"An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS","display_name":"An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2151467224","doi":"https://doi.org/10.1145/1077603.1077630","mag":"2151467224"},"language":"en","primary_location":{"id":"doi:10.1145/1077603.1077630","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1077603.1077630","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 international symposium on Low power electronics and design  - ISLPED '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109275074","display_name":"Steven K. Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Steven K. Hsu","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006348328","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-4220-3346"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0009-0002-3375-2877"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram K. Krishnamurthy","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112875487","display_name":"Shekhar Borkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shekhar Borkar","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5109275074"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.20799099,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"103","last_page":"103"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10361","display_name":"Silicon Carbide Semiconductor Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.8259845972061157},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.666816771030426},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6078752279281616},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48434126377105713},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4045628309249878},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.27684879302978516},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15270116925239563},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.08078140020370483}],"concepts":[{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.8259845972061157},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.666816771030426},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6078752279281616},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48434126377105713},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4045628309249878},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.27684879302978516},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15270116925239563},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.08078140020370483}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1077603.1077630","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1077603.1077630","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 international symposium on Low power electronics and design  - ISLPED '05","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1498618309","https://openalex.org/W2148720570","https://openalex.org/W2160868885"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2042399072","https://openalex.org/W3144620029","https://openalex.org/W2356166161","https://openalex.org/W2155131180","https://openalex.org/W2139082473","https://openalex.org/W1859275911","https://openalex.org/W2130533867","https://openalex.org/W2045163867","https://openalex.org/W2059502833"],"abstract_inverted_index":{"In":[0],"high":[1],"performance":[2,65,122],"microprocessors,":[3],"integer":[4,28],"execution":[5,29],"cores":[6],"are":[7],"one":[8],"of":[9],"the":[10,47,53,79,120],"hottest":[11],"thermal":[12],"spots":[13],"and":[14,24,31,49,100,106],"peak":[15,60],"current/power":[16],"delivery":[17],"limiters.":[18],"This":[19],"paper":[20],"describes":[21],"a":[22],"dual-supply":[23],"dual-threshold":[25],"optimized":[26],"32-bit":[27],"ALU":[30,48],"register":[32,54],"file":[33,55,81],"loop":[34],"for":[35,86],"8.3GHz":[36],"operation":[37],"in":[38],"1.2V,":[39],"90nm":[40],"CMOS":[41],"technology.":[42],"Aggressive":[43],"supply/threshold":[44,51],"scaling":[45],"on":[46,52],"nominal":[50],"enables":[56],"up":[57],"to":[58,114],"25%":[59],"energy":[61],"reduction":[62],"without":[63],"sacrificing":[64],"or":[66],"array":[67],"bit-cells":[68],"stability.":[69],"A":[70],"hybrid":[71],"split-output":[72],"style":[73,117],"CVSL":[74,116],"sequential":[75,95,118],"level":[76],"converter":[77],"at":[78,119],"ALU-register":[80],"interface":[82],"is":[83],"also":[84],"described":[85],"robust,":[87],"DC":[88],"power":[89,105,111],"free":[90],"dual-Vcc":[91],"operation.":[92],"The":[93],"proposed":[94],"occupies":[96],"10%":[97],"smaller":[98],"area,":[99],"saves":[101],"11%":[102],"active":[103],"leakage":[104],"14%":[107],"worst":[108],"case":[109],"switching":[110],"as":[112],"compared":[113],"conventional":[115],"same":[121]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
