{"id":"https://openalex.org/W2161550080","doi":"https://doi.org/10.1145/1065579.1065807","title":"Deterministic approaches to analog performance space exploration (PSE)","display_name":"Deterministic approaches to analog performance space exploration (PSE)","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2161550080","doi":"https://doi.org/10.1145/1065579.1065807","mag":"2161550080"},"language":"en","primary_location":{"id":"doi:10.1145/1065579.1065807","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1065579.1065807","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 42nd annual conference on Design automation  - DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011419637","display_name":"Daniel Mueller-Gritschneder","orcid":"https://orcid.org/0000-0003-0903-631X"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Daniel Mueller","raw_affiliation_strings":["Techn. Univ. Muenchen, Munich, Germany"],"affiliations":[{"raw_affiliation_string":"Techn. Univ. Muenchen, Munich, Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022053055","display_name":"Guido Stehr","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Guido Stehr","raw_affiliation_strings":["Techn. Univ. Muenchen, Munich, Germany"],"affiliations":[{"raw_affiliation_string":"Techn. Univ. Muenchen, Munich, Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033163680","display_name":"Helmut Graeb","orcid":"https://orcid.org/0000-0002-7626-1958"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Helmut Graeb","raw_affiliation_strings":["Techn. Univ. Muenchen, Munich, Germany"],"affiliations":[{"raw_affiliation_string":"Techn. Univ. Muenchen, Munich, Germany","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017567485","display_name":"Ulf Schlichtmann","orcid":"https://orcid.org/0000-0003-4431-7619"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ulf Schlichtmann","raw_affiliation_strings":["Techn. Univ. Muenchen, Munich, Germany"],"affiliations":[{"raw_affiliation_string":"Techn. Univ. Muenchen, Munich, Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5011419637"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.4424,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.95888814,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"869","last_page":"869"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.626640796661377},{"id":"https://openalex.org/keywords/space","display_name":"Space (punctuation)","score":0.5970038771629333},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5850305557250977},{"id":"https://openalex.org/keywords/range","display_name":"Range (aeronautics)","score":0.577019214630127},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5662391781806946},{"id":"https://openalex.org/keywords/space-exploration","display_name":"Space exploration","score":0.4892570972442627},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4832533001899719},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.45390522480010986},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.43688902258872986},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.4193662405014038},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21766245365142822},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14845672249794006},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1027694046497345},{"id":"https://openalex.org/keywords/aerospace-engineering","display_name":"Aerospace engineering","score":0.09426218271255493}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.626640796661377},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.5970038771629333},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5850305557250977},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.577019214630127},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5662391781806946},{"id":"https://openalex.org/C104060986","wikidata":"https://www.wikidata.org/wiki/Q180046","display_name":"Space exploration","level":2,"score":0.4892570972442627},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4832533001899719},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.45390522480010986},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.43688902258872986},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.4193662405014038},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21766245365142822},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14845672249794006},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1027694046497345},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.09426218271255493},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1065579.1065807","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1065579.1065807","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 42nd annual conference on Design automation  - DAC '05","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.95.1070","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.95.1070","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://videos.dac.com/42nd/papers/51_1.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1525529650","https://openalex.org/W1539334032","https://openalex.org/W1550100726","https://openalex.org/W1923938023","https://openalex.org/W1986873938","https://openalex.org/W1996190198","https://openalex.org/W2078592402","https://openalex.org/W2104339053","https://openalex.org/W2106476087","https://openalex.org/W2110224424","https://openalex.org/W2116235542","https://openalex.org/W2116927326","https://openalex.org/W2121112734","https://openalex.org/W2130470045","https://openalex.org/W2132203079","https://openalex.org/W2138396608","https://openalex.org/W2138908842","https://openalex.org/W2141001531","https://openalex.org/W2141964731","https://openalex.org/W2142024558","https://openalex.org/W2143165109","https://openalex.org/W2143256102","https://openalex.org/W2143806010","https://openalex.org/W2144133630","https://openalex.org/W2147849504","https://openalex.org/W2156475541","https://openalex.org/W2162964517","https://openalex.org/W2170626008","https://openalex.org/W2259863082","https://openalex.org/W2470451944"],"related_works":["https://openalex.org/W2383869160","https://openalex.org/W3052481912","https://openalex.org/W4386307087","https://openalex.org/W4323547220","https://openalex.org/W3002866540","https://openalex.org/W4242095216","https://openalex.org/W2076315555","https://openalex.org/W1540027087","https://openalex.org/W2803084856","https://openalex.org/W3092366404"],"abstract_inverted_index":{"Performance":[0],"space":[1,36],"exploration":[2],"(PSE)":[3],"determines":[4],"the":[5,33,58],"range":[6],"of":[7,11,50,57,61,70],"feasible":[8,34],"performance":[9,35],"values":[10],"a":[12,16,47,66,73],"circuit":[13,40],"block":[14],"for":[15,29,45],"given":[17],"topology":[18],"and":[19,42,68],"technology.":[20],"In":[21,64],"this":[22],"paper,":[23],"we":[24],"present":[25],"two":[26],"deterministic":[27],"approaches":[28],"PSE.":[30],"One":[31],"approximates":[32],"based":[37],"on":[38],"linearized":[39],"models":[41],"is":[43,77],"suitable":[44],"investigating":[46],"large":[48],"number":[49],"performances.":[51,63],"The":[52],"other":[53],"one":[54],"computes":[55],"discretizations":[56],"Pareto":[59],"front":[60],"competing":[62],"addition,":[65],"motivation":[67],"application":[69],"PSE":[71],"using":[72],"hierarchical":[74],"design":[75],"example":[76],"presented.":[78]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}