{"id":"https://openalex.org/W2107966189","doi":"https://doi.org/10.1145/1065579.1065792","title":"How accurately can we model timing in a placement engine?","display_name":"How accurately can we model timing in a placement engine?","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2107966189","doi":"https://doi.org/10.1145/1065579.1065792","mag":"2107966189"},"language":"en","primary_location":{"id":"doi:10.1145/1065579.1065792","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1065579.1065792","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 42nd annual conference on Design automation  - DAC '05","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110217522","display_name":"Amit Chowdhary","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Chowdhary","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041367930","display_name":"Karthik Rajagopal","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Karthik Rajagopal","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111722094","display_name":"Satish Venkatesan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satish Venkatesan","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041945124","display_name":"Tung Cao","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tung Cao","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081182844","display_name":"Vladimir Tiourin","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vladimir Tiourin","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041937250","display_name":"Yegna Parasuram","orcid":null},"institutions":[{"id":"https://openalex.org/I4210147298","display_name":"Sierra Engineering (United States)","ror":"https://ror.org/05kdrns38","country_code":"US","type":"company","lineage":["https://openalex.org/I4210147298"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yegna Parasuram","raw_affiliation_strings":["Sierra Design Automation, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sierra Design Automation, Santa Clara, CA","institution_ids":["https://openalex.org/I4210147298"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087564075","display_name":"Bill Halpin","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bill Halpin","raw_affiliation_strings":["Synplicity, Inc., Sunnyvale, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synplicity, Inc., Sunnyvale, CA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":62,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"801","last_page":"801"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.7989093661308289},{"id":"https://openalex.org/keywords/timer","display_name":"Timer","score":0.747695803642273},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7165154218673706},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5357866287231445},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.5184347629547119},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.47064775228500366},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4573158919811249},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.44519832730293274},{"id":"https://openalex.org/keywords/optimization-problem","display_name":"Optimization problem","score":0.4246307611465454},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.16503077745437622},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16347452998161316}],"concepts":[{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7989093661308289},{"id":"https://openalex.org/C2776633867","wikidata":"https://www.wikidata.org/wiki/Q186612","display_name":"Timer","level":3,"score":0.747695803642273},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7165154218673706},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5357866287231445},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.5184347629547119},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.47064775228500366},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4573158919811249},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.44519832730293274},{"id":"https://openalex.org/C137836250","wikidata":"https://www.wikidata.org/wiki/Q984063","display_name":"Optimization problem","level":2,"score":0.4246307611465454},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16503077745437622},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16347452998161316},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1065579.1065792","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1065579.1065792","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 42nd annual conference on Design automation  - DAC '05","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1984588379","https://openalex.org/W2003764518","https://openalex.org/W2108411416","https://openalex.org/W2117793659","https://openalex.org/W2119248453","https://openalex.org/W2123455796","https://openalex.org/W2163632212","https://openalex.org/W2163763728"],"related_works":["https://openalex.org/W2360439717","https://openalex.org/W2388292776","https://openalex.org/W2765214557","https://openalex.org/W2361181213","https://openalex.org/W1031622928","https://openalex.org/W2350005463","https://openalex.org/W2347554032","https://openalex.org/W4293162581","https://openalex.org/W1987947034","https://openalex.org/W2380195243"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,12,31,47,54,91,132,137,148],"novel":[4],"placement":[5,40,67,82],"algorithm":[6,41],"for":[7,131],"timing":[8,21,28,34,44,50,58,72,88,182],"optimization":[9,26,83],"based":[10,85],"on":[11,69,86,129],"new":[13,103],"and":[14,120,145],"powerful":[15],"concept,":[16],"which":[17,97,173],"we":[18,36],"term":[19],"differential":[20,57,87],"analysis.":[22],"Recognizing":[23],"that":[24,42,61,108,141,157,175],"accurate":[25],"requires":[27],"information":[29,45],"from":[30,46,73,136],"signoff":[32,48,75],"static":[33,49],"analyzer,":[35],"propose":[37,53],"an":[38,80,116,168],"incremental":[39,81],"uses":[43],"engine.":[51],"We":[52,77,154],"set":[55,133],"of":[56,66,118,134,160,171],"analysis":[59,89],"equations":[60],"accurately":[62],"capture":[63],"the":[64,74,102,109,121],"effect":[65],"perturbations":[68],"changes":[70],"in":[71],"timer.":[76],"have":[78],"formulated":[79],"problem":[84,96],"as":[90],"single":[92],"linear":[93],"programming":[94],"(LP)":[95],"is":[98],"solved":[99],"to":[100],"generate":[101],"timing-optimized":[104],"placement.Our":[105],"experiments":[106],"show":[107,156],"worst":[110],"negative":[111,123],"slack":[112,124],"(WNS)":[113],"improves":[114,126],"by":[115,127,147],"average":[117,130,169],"30%":[119],"total":[122],"(TNS)":[125],"33%":[128],"circuits":[135],"3.0":[138],"GHz":[139],"microprocessor":[140],"were":[142],"already":[143],"synthesized":[144],"placed":[146],"leading":[149],"industrial":[150],"physical":[151],"synthesis":[152],"tool.":[153],"also":[155],"multiple":[158],"iterations":[159],"our":[161,176],"engine":[162],"give":[163],"further":[164],"TNS":[165],"improvements":[166],"-":[167],"improvement":[170],"51%,":[172],"implies":[174],"placer":[177],"will":[178],"significantly":[179],"speed":[180],"up":[181],"convergence.":[183]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}