{"id":"https://openalex.org/W2161858973","doi":"https://doi.org/10.1145/1065579.1065759","title":"TCAM enabled on-chip logic minimization","display_name":"TCAM enabled on-chip logic minimization","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2161858973","doi":"https://doi.org/10.1145/1065579.1065759","mag":"2161858973"},"language":"en","primary_location":{"id":"doi:10.1145/1065579.1065759","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1065579.1065759","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 42nd annual conference on Design automation  - DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103604917","display_name":"Seraj Ahmad","orcid":null},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Seraj Ahmad","raw_affiliation_strings":["Texas A & M University, College Station, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A & M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103702897","display_name":"Rabi Mahapatra","orcid":"https://orcid.org/0000-0003-1702-8045"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rabi Mahapatra","raw_affiliation_strings":["Texas A & M University, College Station, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A & M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.23704543,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"678","last_page":"678"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.987500011920929,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6639668941497803},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5498733520507812},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5469269752502441},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5317505598068237},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.49480074644088745},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4577367305755615},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45419105887413025},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3644145727157593},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35506922006607056},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3529059886932373},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17838573455810547},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14103838801383972},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10525083541870117}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6639668941497803},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5498733520507812},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5469269752502441},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5317505598068237},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.49480074644088745},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4577367305755615},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45419105887413025},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3644145727157593},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35506922006607056},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3529059886932373},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17838573455810547},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14103838801383972},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10525083541870117}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1065579.1065759","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1065579.1065759","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 42nd annual conference on Design automation  - DAC '05","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.575.3873","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.575.3873","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.york.ac.uk/rts/docs/DAC-1964-2005/papers/2005/dac05/pdffiles/p678.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1573997715","https://openalex.org/W1873097804","https://openalex.org/W2028265666","https://openalex.org/W2104227023","https://openalex.org/W2109041721","https://openalex.org/W2135483243","https://openalex.org/W2149949040","https://openalex.org/W2151970267","https://openalex.org/W2331644287"],"related_works":["https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W2115579119","https://openalex.org/W2023708001","https://openalex.org/W2136854845","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W4246018535","https://openalex.org/W2789349722","https://openalex.org/W1985308002"],"abstract_inverted_index":{"This":[0],"paper":[1,33],"presents":[2,34],"an":[3,8],"efficient":[4,24],"hardware":[5,49],"architecture":[6,15],"of":[7,38,55,75],"on-chip":[9,29,40],"logic":[10],"minimization":[11,30],"coprocessor.":[12],"The":[13,32],"proposed":[14],"employs":[16],"TCAM":[17,84],"cells":[18],"to":[19,51],"provide":[20],"fastest":[21],"and":[22,42,60,68,72],"memory":[23],"implementation":[25],"suitable":[26],"for":[27],"emerging":[28],"applications.":[31],"a":[35,73],"detailed":[36],"design":[37],"the":[39],"minimizer":[41],"shows":[43],"that":[44],"it":[45],"requires":[46],"very":[47],"little":[48],"resources":[50],"achieve":[52],"acceptable":[53],"quality":[54],"minimization.":[56],"An":[57],"incremental":[58],"insertion":[59],"bulk":[61],"deletion":[62],"is":[63],"achieved":[64],"in":[65,78],"0.25":[66],"\u03bcs":[67],"3.8":[69],"ms":[70,80],"respectively":[71],"compaction":[74],"100000":[76],"entries":[77],"25":[79],"using":[81],"just":[82],"300":[83],"entries.":[85]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
