{"id":"https://openalex.org/W2127322963","doi":"https://doi.org/10.1145/1065579.1065729","title":"Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements","display_name":"Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2127322963","doi":"https://doi.org/10.1145/1065579.1065729","mag":"2127322963"},"language":"en","primary_location":{"id":"doi:10.1145/1065579.1065729","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1065579.1065729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 42nd annual conference on Design automation  - DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088398746","display_name":"Sven Heithecker","orcid":null},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Sven Heithecker","raw_affiliation_strings":["Technical University of Braunschweig","Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Technical University of Braunschweig","institution_ids":["https://openalex.org/I94509681"]},{"raw_affiliation_string":"Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075507551","display_name":"Rolf Ernst","orcid":"https://orcid.org/0000-0003-2414-9566"},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rolf Ernst","raw_affiliation_strings":["Technical University of Braunschweig","Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Technical University of Braunschweig","institution_ids":["https://openalex.org/I94509681"]},{"raw_affiliation_string":"Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5088398746"],"corresponding_institution_ids":["https://openalex.org/I94509681"],"apc_list":null,"apc_paid":null,"fwci":3.3741,"has_fulltext":false,"cited_by_count":53,"citation_normalized_percentile":{"value":0.9335637,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"575","last_page":"575"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8211262226104736},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6471680402755737},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6423998475074768},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6356165409088135},{"id":"https://openalex.org/keywords/quality-of-service","display_name":"Quality of service","score":0.6305240988731384},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.5653383135795593},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5540187954902649},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5269306898117065},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.5228388905525208},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5027360916137695},{"id":"https://openalex.org/keywords/video-decoder","display_name":"Video decoder","score":0.4600526988506317},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.44880372285842896},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.42203885316848755},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3033602237701416},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2430124282836914},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.21336692571640015},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.13512983918190002},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09314391016960144}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8211262226104736},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6471680402755737},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6423998475074768},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6356165409088135},{"id":"https://openalex.org/C5119721","wikidata":"https://www.wikidata.org/wiki/Q220501","display_name":"Quality of service","level":2,"score":0.6305240988731384},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.5653383135795593},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5540187954902649},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5269306898117065},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.5228388905525208},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5027360916137695},{"id":"https://openalex.org/C2776580754","wikidata":"https://www.wikidata.org/wiki/Q25098614","display_name":"Video decoder","level":3,"score":0.4600526988506317},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.44880372285842896},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.42203885316848755},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3033602237701416},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2430124282836914},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.21336692571640015},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.13512983918190002},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09314391016960144},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1065579.1065729","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1065579.1065729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 42nd annual conference on Design automation  - DAC '05","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1585223597","https://openalex.org/W1594610643","https://openalex.org/W1994115836","https://openalex.org/W2015717967","https://openalex.org/W2034147186","https://openalex.org/W2070174169","https://openalex.org/W2096506606","https://openalex.org/W2114295495","https://openalex.org/W2115172404","https://openalex.org/W2117285153","https://openalex.org/W2132678462"],"related_works":["https://openalex.org/W2543262377","https://openalex.org/W2382635124","https://openalex.org/W2082585011","https://openalex.org/W2382603124","https://openalex.org/W2373671989","https://openalex.org/W2014902372","https://openalex.org/W4311218570","https://openalex.org/W2348758434","https://openalex.org/W2382533953","https://openalex.org/W4236019237"],"abstract_inverted_index":{"Today":[0],"high-end":[1,115],"video":[2,64,72,116],"and":[3,66,93],"multimedia":[4],"processing":[5],"applications":[6],"require":[7],"huge":[8],"amounts":[9],"of":[10,17,51,88,121],"memory.":[11],"For":[12],"cost":[13],"reasons,":[14],"the":[15,107,119],"usage":[16],"conventional":[18],"dynamic":[19],"RAM":[20],"(SDRAM)":[21],"is":[22,28,40],"preferred.":[23],"However,":[24],"SDRAM":[25],"access":[26,35],"optimization":[27],"a":[29,44,86,89],"complex":[30],"task,":[31],"especially":[32],"if":[33],"multistream":[34],"with":[36,111],"different":[37],"QoS":[38,80],"requirements":[39,54,81],"involved.":[41],"In":[42],"[8],":[43],"multi-stream":[45],"DDR-SDRAM":[46],"controller":[47],"IP":[48],"covering":[49],"combinations":[50],"low":[52],"latency":[53],"for":[55,62,71],"processor":[56],"cache":[57],"access,":[58],"hard":[59,67],"realtime":[60],"constraints":[61],"periodic":[63],"signals":[65],"real-time":[68],"bursty":[69],"accesses":[70],"coprocessors":[73],"was":[74],"described.":[75],"To":[76],"handle":[77],"these":[78],"contradictory":[79],"at":[82],"high":[83],"system":[84],"performance,":[85],"combination":[87],"2-stage":[90],"scheduling":[91],"algorithm":[92],"static":[94],"priorities":[95],"were":[96],"used.":[97],"This":[98],"paper":[99],"describes":[100],"an":[101,112],"additional":[102],"flow":[103],"control":[104],"which":[105],"enhances":[106],"overall":[108],"performance.":[109],"Experiments":[110],"FPGA":[113],"based":[114],"platform":[117],"demonstrate":[118],"superiority":[120],"this":[122],"architecture.":[123]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}