{"id":"https://openalex.org/W2111978289","doi":"https://doi.org/10.1145/1057661.1057769","title":"LiPaR","display_name":"LiPaR","publication_year":2005,"publication_date":"2005-04-17","ids":{"openalex":"https://openalex.org/W2111978289","doi":"https://doi.org/10.1145/1057661.1057769","mag":"2111978289"},"language":"en","primary_location":{"id":"doi:10.1145/1057661.1057769","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057769","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077577071","display_name":"B. Sethuraman","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Balasubramanian Sethuraman","raw_affiliation_strings":["University of Cincinnati, Cincinnati, OH","University of CIncinnati, CIncinnati, OH"],"affiliations":[{"raw_affiliation_string":"University of Cincinnati, Cincinnati, OH","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"University of CIncinnati, CIncinnati, OH","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055230935","display_name":"Prasun Bhattacharya","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prasun Bhattacharya","raw_affiliation_strings":["University of Cincinnati, Cincinnati, OH","University of CIncinnati, CIncinnati, OH"],"affiliations":[{"raw_affiliation_string":"University of Cincinnati, Cincinnati, OH","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"University of CIncinnati, CIncinnati, OH","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101630991","display_name":"Jawad Khan","orcid":"https://orcid.org/0000-0001-6911-3546"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jawad Khan","raw_affiliation_strings":["University of Cincinnati, Cincinnati, OH","University of CIncinnati, CIncinnati, OH"],"affiliations":[{"raw_affiliation_string":"University of Cincinnati, Cincinnati, OH","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"University of CIncinnati, CIncinnati, OH","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040975645","display_name":"Ranga Vemuri","orcid":"https://orcid.org/0000-0002-4903-2746"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ranga Vemuri","raw_affiliation_strings":["University of Cincinnati, Cincinnati, OH","University of CIncinnati, CIncinnati, OH"],"affiliations":[{"raw_affiliation_string":"University of Cincinnati, Cincinnati, OH","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"University of CIncinnati, CIncinnati, OH","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5077577071"],"corresponding_institution_ids":["https://openalex.org/I63135867"],"apc_list":null,"apc_paid":null,"fwci":7.0078,"has_fulltext":false,"cited_by_count":77,"citation_normalized_percentile":{"value":0.97247277,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"452","last_page":"457"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.989799976348877,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9894999861717224,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7176874876022339},{"id":"https://openalex.org/keywords/header","display_name":"Header","score":0.6504293084144592},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.6058598160743713},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5523769855499268},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.5458143949508667},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.485676646232605},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.473332941532135},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4708912968635559},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.4632742404937744},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4578614830970764},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43359941244125366},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4203298091888428},{"id":"https://openalex.org/keywords/routing-table","display_name":"Routing table","score":0.4174734950065613},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.25637921690940857},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08995518088340759},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08855932950973511}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7176874876022339},{"id":"https://openalex.org/C48105269","wikidata":"https://www.wikidata.org/wiki/Q1141160","display_name":"Header","level":2,"score":0.6504293084144592},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.6058598160743713},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5523769855499268},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.5458143949508667},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.485676646232605},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.473332941532135},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4708912968635559},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.4632742404937744},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4578614830970764},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43359941244125366},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4203298091888428},{"id":"https://openalex.org/C184896649","wikidata":"https://www.wikidata.org/wiki/Q290066","display_name":"Routing table","level":4,"score":0.4174734950065613},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.25637921690940857},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08995518088340759},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08855932950973511}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1057661.1057769","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057769","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W122228617","https://openalex.org/W186740131","https://openalex.org/W1497140550","https://openalex.org/W1561157983","https://openalex.org/W1609287256","https://openalex.org/W2063475318","https://openalex.org/W2119677480","https://openalex.org/W2123184444","https://openalex.org/W2160457411","https://openalex.org/W2160642395","https://openalex.org/W2163590199","https://openalex.org/W2165666359","https://openalex.org/W2534992321","https://openalex.org/W3169463464","https://openalex.org/W6629587454"],"related_works":["https://openalex.org/W2171597999","https://openalex.org/W2189136227","https://openalex.org/W1866537546","https://openalex.org/W630850086","https://openalex.org/W3200508093","https://openalex.org/W4372053344","https://openalex.org/W3193978431","https://openalex.org/W2481444631","https://openalex.org/W2320225356","https://openalex.org/W2032055818"],"abstract_inverted_index":{"Present":[0],"day":[1],"technology":[2],"for":[3,176,193],"ASICs":[4],"supports":[5],"Networks-on-Chip":[6],"designs":[7],"which":[8,93],"can":[9,21,64,94,147],"have":[10],"100":[11],"million":[12,26],"gates":[13,27],"on":[14],"a":[15,40,56,90,157,164,180],"single":[16],"chip.":[17],"The":[18,135],"latest":[19],"FPGAs":[20],"support":[22,95],"only":[23,109],"about":[24],"10":[25],"to":[28,38,55],"accomodate":[29],"all":[30],"logic":[31,69,128,178],"and":[32,126,133,143,151,189,195],"the":[33,46,50,61,68,72,75,82,101,144,173,177,187],"associated":[34],"routing.":[35],"In":[36,85],"order":[37],"implement":[39,89,156],"competitive":[41],"NoC":[42],"architecture":[43],"in":[44,123,131,179],"FP-GAs,":[45],"area":[47,63,79,106,132,166,174],"occupied":[48],"by":[49,67],"network":[51,162],"should":[52],"be":[53,65],"kept":[54],"minimum.":[57],"This":[58],"ensures":[59],"that":[60],"maximum":[62],"utilized":[66],"while":[70],"maintaining":[71],"performance":[73,196],"of":[74,108,118,168,172],"router":[76,92,188],"network.":[77],"Reducing":[78],"also":[80,155],"reduces":[81],"power":[83,194],"consumption.":[84],"this":[86],"paper,":[87],"we":[88],"parallel":[91],"five":[96],"simultaneous":[97],"routing":[98,125],"requests":[99],"at":[100],"same":[102],"time":[103],"with":[104,163],"an":[105],"overhead":[107,137,167],"352":[110],"Xilinx":[111],"Virtex-II":[112,181],"Pro":[113,182],"FPGA":[114],"slices":[115],"(2.":[116],"57%":[117],"XC2VP30).":[119],"We":[120,154,185],"introduce":[121],"optimizations":[122],"XY":[124],"decoding":[127],"thereby":[129],"gaining":[130],"performance.":[134],"header":[136],"is":[138],"8":[139],"bits":[140],"per":[141],"packet":[142,145],"size":[146],"vary":[148],"between":[149],"16":[150],"128":[152],"bits.":[153],"3":[158,160],"x":[159],"mesh":[161,191],"total":[165],"28%":[169],"leaving":[170],"72%":[171],"available":[175],"XC2VP30":[183],"device.":[184],"characterize":[186],"several":[190],"networks":[192],"parameters.":[197]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":12}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
