{"id":"https://openalex.org/W2106288082","doi":"https://doi.org/10.1145/1057661.1057758","title":"Characterization of monotonic static CMOS gates in a 65nm technology","display_name":"Characterization of monotonic static CMOS gates in a 65nm technology","publication_year":2005,"publication_date":"2005-04-17","ids":{"openalex":"https://openalex.org/W2106288082","doi":"https://doi.org/10.1145/1057661.1057758","mag":"2106288082"},"language":"en","primary_location":{"id":"doi:10.1145/1057661.1057758","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057758","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002661228","display_name":"Ali Foroush Bastani","orcid":"https://orcid.org/0000-0003-4431-7483"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ali Bastani","raw_affiliation_strings":["Columbia University, New York, NY","Columbia University, New York, NY;"],"affiliations":[{"raw_affiliation_string":"Columbia University, New York, NY","institution_ids":["https://openalex.org/I78577930"]},{"raw_affiliation_string":"Columbia University, New York, NY;","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000640914","display_name":"C. Zukowski","orcid":null},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles A. Zukowski","raw_affiliation_strings":["Columbia University, New York, NY","Columbia University, New York, NY;"],"affiliations":[{"raw_affiliation_string":"Columbia University, New York, NY","institution_ids":["https://openalex.org/I78577930"]},{"raw_affiliation_string":"Columbia University, New York, NY;","institution_ids":["https://openalex.org/I78577930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5002661228"],"corresponding_institution_ids":["https://openalex.org/I78577930"],"apc_list":null,"apc_paid":null,"fwci":0.7114,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.74332207,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"408","last_page":"411"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8710232973098755},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.7683599591255188},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6817737817764282},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5904598236083984},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.5885709524154663},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.551737904548645},{"id":"https://openalex.org/keywords/gate-equivalent","display_name":"Gate equivalent","score":0.531378448009491},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5272791981697083},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.4707674980163574},{"id":"https://openalex.org/keywords/monotonic-function","display_name":"Monotonic function","score":0.46250221133232117},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.4372365176677704},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.4297701120376587},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4156262278556824},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.37911123037338257},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3330986797809601},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.3290206491947174},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.3034682869911194},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29647302627563477},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.25261443853378296},{"id":"https://openalex.org/keywords/gate-oxide","display_name":"Gate oxide","score":0.24942293763160706},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14940562844276428},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14450132846832275},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09341517090797424}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8710232973098755},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.7683599591255188},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6817737817764282},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5904598236083984},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5885709524154663},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.551737904548645},{"id":"https://openalex.org/C60697091","wikidata":"https://www.wikidata.org/wiki/Q5527009","display_name":"Gate equivalent","level":5,"score":0.531378448009491},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5272791981697083},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.4707674980163574},{"id":"https://openalex.org/C72169020","wikidata":"https://www.wikidata.org/wiki/Q194404","display_name":"Monotonic function","level":2,"score":0.46250221133232117},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.4372365176677704},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.4297701120376587},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4156262278556824},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.37911123037338257},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3330986797809601},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3290206491947174},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.3034682869911194},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29647302627563477},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.25261443853378296},{"id":"https://openalex.org/C2361726","wikidata":"https://www.wikidata.org/wiki/Q5527031","display_name":"Gate oxide","level":4,"score":0.24942293763160706},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14940562844276428},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14450132846832275},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09341517090797424},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1057661.1057758","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057758","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8500000238418579,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2145843023","https://openalex.org/W2159683499","https://openalex.org/W2163955501"],"related_works":["https://openalex.org/W4361799621","https://openalex.org/W2136637128","https://openalex.org/W1496213896","https://openalex.org/W1017999001","https://openalex.org/W2024713617","https://openalex.org/W2804171474","https://openalex.org/W2760870732","https://openalex.org/W2791832526","https://openalex.org/W2118713399","https://openalex.org/W2891188466"],"abstract_inverted_index":{"This":[0],"paper":[1],"reviews":[2],"the":[3,35,47,64,68,71,83],"use":[4],"of":[5,73],"skewed":[6],"monotonic":[7],"static":[8,53],"CMOS":[9,44],"logic":[10],"gates":[11],"in":[12,39,52,60],"scaled":[13],"technologies":[14],"where":[15],"gate":[16,48,84],"leakage":[17,85],"currents":[18],"become":[19],"significant.":[20],"High-level":[21],"tradeoffs":[22,38,65],"and":[23,28,70],"synthesis":[24],"approaches":[25],"are":[26,31,56,75,79],"discussed,":[27],"some":[29],"experiments":[30],"constructed":[32],"to":[33],"evaluate":[34],"gate-level":[36],"performance":[37],"a":[40],"hypothetical":[41],"standard":[42],"65nm":[43],"technology.":[45],"At":[46],"level,":[49],"significant":[50],"improvements":[51],"power":[54],"consumption":[55],"possible":[57],"without":[58],"reduction":[59],"evaluation":[61],"delays,":[62],"but":[63],"vary":[66],"as":[67,82],"conditions":[69],"amount":[72],"skewing":[74],"changed.":[76],"NAND":[77],"forms":[78],"still":[80],"preferred":[81],"grows.":[86]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}