{"id":"https://openalex.org/W2158781448","doi":"https://doi.org/10.1145/1057661.1057756","title":"Exploiting PSL standard assertions in a theorem-proving-based verification environment","display_name":"Exploiting PSL standard assertions in a theorem-proving-based verification environment","publication_year":2005,"publication_date":"2005-04-17","ids":{"openalex":"https://openalex.org/W2158781448","doi":"https://doi.org/10.1145/1057661.1057756","mag":"2158781448"},"language":"en","primary_location":{"id":"doi:10.1145/1057661.1057756","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057756","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100774710","display_name":"Young Sik Kim","orcid":"https://orcid.org/0000-0003-4114-4935"},"institutions":[{"id":"https://openalex.org/I70983195","display_name":"Syracuse University","ror":"https://ror.org/025r5qe02","country_code":"US","type":"education","lineage":["https://openalex.org/I70983195"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Youngsik Kim","raw_affiliation_strings":["Syracuse University, Syracuse, New York"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Syracuse University, Syracuse, New York","institution_ids":["https://openalex.org/I70983195"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040185383","display_name":"Parija Sule","orcid":null},"institutions":[{"id":"https://openalex.org/I70983195","display_name":"Syracuse University","ror":"https://ror.org/025r5qe02","country_code":"US","type":"education","lineage":["https://openalex.org/I70983195"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Parija Sule","raw_affiliation_strings":["Syracuse University, Syracuse, New York"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Syracuse University, Syracuse, New York","institution_ids":["https://openalex.org/I70983195"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112153184","display_name":"Nazanin Mansouri","orcid":null},"institutions":[{"id":"https://openalex.org/I70983195","display_name":"Syracuse University","ror":"https://ror.org/025r5qe02","country_code":"US","type":"education","lineage":["https://openalex.org/I70983195"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nazanin Mansouri","raw_affiliation_strings":["Syracuse University, Syracuse, New York"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Syracuse University, Syracuse, New York","institution_ids":["https://openalex.org/I70983195"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I70983195"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.25449912,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"400","last_page":"403"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9857000112533569,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9857000112533569,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9771999716758728,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.9700000286102295,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automated-theorem-proving","display_name":"Automated theorem proving","score":0.8033674955368042},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7310964465141296},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.6961889266967773},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6906206011772156},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6226977705955505},{"id":"https://openalex.org/keywords/hol","display_name":"HOL","score":0.5554710030555725},{"id":"https://openalex.org/keywords/predicate","display_name":"Predicate (mathematical logic)","score":0.5076993703842163},{"id":"https://openalex.org/keywords/assertion","display_name":"Assertion","score":0.49206727743148804},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.45858973264694214},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.41126513481140137},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.38759708404541016},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.08590772747993469}],"concepts":[{"id":"https://openalex.org/C206880738","wikidata":"https://www.wikidata.org/wiki/Q431667","display_name":"Automated theorem proving","level":2,"score":0.8033674955368042},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7310964465141296},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.6961889266967773},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6906206011772156},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6226977705955505},{"id":"https://openalex.org/C17435882","wikidata":"https://www.wikidata.org/wiki/Q17030435","display_name":"HOL","level":2,"score":0.5554710030555725},{"id":"https://openalex.org/C140146324","wikidata":"https://www.wikidata.org/wiki/Q1144319","display_name":"Predicate (mathematical logic)","level":2,"score":0.5076993703842163},{"id":"https://openalex.org/C40422974","wikidata":"https://www.wikidata.org/wiki/Q741248","display_name":"Assertion","level":2,"score":0.49206727743148804},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.45858973264694214},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.41126513481140137},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.38759708404541016},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.08590772747993469},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1057661.1057756","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057756","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6700000166893005,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1584721038","https://openalex.org/W1605324301","https://openalex.org/W1797377815","https://openalex.org/W2126691011","https://openalex.org/W2155155782"],"related_works":["https://openalex.org/W2534028225","https://openalex.org/W1497011154","https://openalex.org/W4206694237","https://openalex.org/W2724703556","https://openalex.org/W3196544792","https://openalex.org/W1504680642","https://openalex.org/W2519051298","https://openalex.org/W1521746323","https://openalex.org/W2166178773","https://openalex.org/W1606979385"],"abstract_inverted_index":{"Assertion-based":[0],"design":[1,19,48,75],"is":[2],"becoming":[3],"more":[4],"widely":[5],"used":[6],"in":[7,21],"industry.":[8],"However,":[9],"little":[10],"has":[11],"been":[12],"done":[13],"to":[14],"take":[15],"advantage":[16],"of":[17,35,46,60,65,87],"existing":[18,47],"assertions":[20,81],"the":[22,36,58,84,88,102],"theorem-proving":[23,38],"verification":[24,40,77,95],"environments.":[25],"In":[26],"this":[27],"paper,":[28],"we":[29],"present":[30],"our":[31],"work":[32],"on":[33],"development":[34],"semi-automated":[37],"based":[39],"system":[41],"ROVERIFIC":[42,67],"that":[43,56],"makes":[44],"use":[45],"assertions.":[49],"We":[50],"have":[51],"defined":[52],"generic":[53],"predicate":[54],"templates":[55],"capture":[57],"semantics":[59],"PSL,":[61],"and":[62,71,79],"a":[63,74],"subset":[64],"Verilog.":[66],"uses":[68],"these":[69],"templates,":[70],"automatically":[72],"compiles":[73],"under":[76],"(Verilog)":[78],"its":[80],"(PSL)":[82],"into":[83],"higher-order":[85],"predicates":[86],"PVS":[89],"[11]":[90],"theorem":[91],"proving":[92,101],"system.":[93],"Design":[94],"can":[96],"be":[97],"subsequently":[98],"conducted":[99],"by":[100],"correctness":[103],"properties.":[104]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}