{"id":"https://openalex.org/W2160409339","doi":"https://doi.org/10.1145/1057661.1057711","title":"Tile-based design of a serial memory in QCA","display_name":"Tile-based design of a serial memory in QCA","publication_year":2005,"publication_date":"2005-04-17","ids":{"openalex":"https://openalex.org/W2160409339","doi":"https://doi.org/10.1145/1057661.1057711","mag":"2160409339"},"language":"en","primary_location":{"id":"doi:10.1145/1057661.1057711","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057711","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044064806","display_name":"V. Vankamamidi","orcid":null},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"V. Vankamamidi","raw_affiliation_strings":["Northeastern University, Boston, MA"],"affiliations":[{"raw_affiliation_string":"Northeastern University, Boston, MA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048232172","display_name":"Marco Ottavi","orcid":"https://orcid.org/0000-0002-5064-7342"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Ottavi","raw_affiliation_strings":["Northeastern University, Boston, MA"],"affiliations":[{"raw_affiliation_string":"Northeastern University, Boston, MA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001979328","display_name":"Fabrizio Lombardi","orcid":"https://orcid.org/0000-0003-3152-3245"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. Lombardi","raw_affiliation_strings":["Northeastern University, Boston, MA"],"affiliations":[{"raw_affiliation_string":"Northeastern University, Boston, MA","institution_ids":["https://openalex.org/I12912129"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5044064806"],"corresponding_institution_ids":["https://openalex.org/I12912129"],"apc_list":null,"apc_paid":null,"fwci":3.1622,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.91790446,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"75","issue":null,"first_page":"201","last_page":"206"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.983299970626831,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7637609243392944},{"id":"https://openalex.org/keywords/quantum-cellular-automaton","display_name":"Quantum cellular automaton","score":0.48508420586586},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4649558961391449},{"id":"https://openalex.org/keywords/concatenation","display_name":"Concatenation (mathematics)","score":0.4637627601623535},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.44632551074028015},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.44305628538131714},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4101514220237732},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.408974826335907},{"id":"https://openalex.org/keywords/cellular-automaton","display_name":"Cellular automaton","score":0.38301414251327515},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3521154224872589},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34843897819519043},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3309412896633148},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.1439356505870819},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1337776780128479}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7637609243392944},{"id":"https://openalex.org/C68576872","wikidata":"https://www.wikidata.org/wiki/Q4893239","display_name":"Quantum cellular automaton","level":3,"score":0.48508420586586},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4649558961391449},{"id":"https://openalex.org/C87619178","wikidata":"https://www.wikidata.org/wiki/Q126002","display_name":"Concatenation (mathematics)","level":2,"score":0.4637627601623535},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.44632551074028015},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.44305628538131714},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4101514220237732},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.408974826335907},{"id":"https://openalex.org/C35527583","wikidata":"https://www.wikidata.org/wiki/Q189156","display_name":"Cellular automaton","level":2,"score":0.38301414251327515},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3521154224872589},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34843897819519043},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3309412896633148},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.1439356505870819},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1337776780128479},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1057661.1057711","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057711","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:art.torvergata.it:2108/93718","is_oa":false,"landing_page_url":"http://hdl.handle.net/2108/93718","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W116782577","https://openalex.org/W1969293354","https://openalex.org/W1998327734","https://openalex.org/W2059030116","https://openalex.org/W2064575027","https://openalex.org/W2160210493","https://openalex.org/W2165354638"],"related_works":["https://openalex.org/W4242495027","https://openalex.org/W2561005478","https://openalex.org/W4293159259","https://openalex.org/W3093911585","https://openalex.org/W1494152240","https://openalex.org/W2907563276","https://openalex.org/W2136268150","https://openalex.org/W2087144150","https://openalex.org/W4389371524","https://openalex.org/W2965383127"],"abstract_inverted_index":{"Quantum-dot":[0],"Cellula":[1],"Automata":[2],"(QCA)":[3],"has":[4],"been":[5],"widely":[6],"advocated":[7],"as":[8,73],"a":[9,54,92,101,113,119,138,149],"new":[10,68],"device":[11],"architecture":[12,58,63],"fo":[13],"nano":[14],"technology.":[15],"QCA":[16,34,60,85,135],"systems":[17],"require":[18],"extremely":[19],"low":[20],"power":[21],"together":[22],"with":[23,156],"the":[24,43,76,82,96,131,134],"potential":[25],"for":[26,38,59],"high":[27],"density":[28],"and":[29,78,99,130],"regularity.":[30],"These":[31],"features":[32],"make":[33],"an":[35],"attractive":[36],"technology":[37],"manufacturing":[39],"memories":[40],"in":[41,75,95,137,148,152],"which":[42,108],"paradigm":[44,86],"of":[45,81,87,115,133,143],"memory-in-motion":[46,88],"can":[47],"be":[48],"fully":[49],"exploited.":[50],"This":[51,62,146],"paper":[52],"proposes":[53],"novel":[55,93],"serial":[56,158],"memory":[57,103,128],"implementation.":[61],"is":[64,89,105,110,141],"based":[65],"on":[66],"utilizing":[67,118],"building":[69],"blocks":[70],"(referred":[71],"to":[72],"tiles)":[74],"storage":[77,97],"input/output":[79],"circuitry":[80],"memory.":[83],"The":[84],"accomplished":[90],"using":[91],"arrangement":[94],"loop":[98],"timing/clocking;":[100],"three-zone":[102],"tile":[104],"proposed":[106],"by":[107,117],"information":[109],"moved":[111],"across":[112],"concatenation":[114],"tiles":[116],"two-level":[120],"clocking":[121,139,153],"mechanism.":[122],"Clocking":[123],"zones":[124,154],"are":[125],"shared":[126],"between":[127],"cells":[129],"length":[132],"line":[136],"zone":[140],"independent":[142],"word":[144],"size.":[145],"results":[147],"substantial":[150],"eduction":[151],"compared":[155],"previous":[157],"memories.":[159]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
