{"id":"https://openalex.org/W2146115382","doi":"https://doi.org/10.1145/1057661.1057681","title":"Exact minimum-width transistor placement without dual constraint for CMOS cells","display_name":"Exact minimum-width transistor placement without dual constraint for CMOS cells","publication_year":2005,"publication_date":"2005-04-17","ids":{"openalex":"https://openalex.org/W2146115382","doi":"https://doi.org/10.1145/1057661.1057681","mag":"2146115382"},"language":"en","primary_location":{"id":"doi:10.1145/1057661.1057681","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057681","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007028121","display_name":"Tetsuya Iizuka","orcid":"https://orcid.org/0000-0002-1512-4714"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Tetsuya Iizuka","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5007028121"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.7114,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.75224479,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"74","last_page":"77"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7667037844657898},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7103573679924011},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.6109409332275391},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.5449777841567993},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.512054979801178},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.47858595848083496},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.4731762707233429},{"id":"https://openalex.org/keywords/type","display_name":"Type (biology)","score":0.4110153019428253},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3705425262451172},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33955660462379456},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33556878566741943},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3280487060546875},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2395494282245636},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21568256616592407},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1907556653022766},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.14147493243217468},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10349756479263306},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.06615626811981201}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7667037844657898},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7103573679924011},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.6109409332275391},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.5449777841567993},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.512054979801178},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.47858595848083496},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.4731762707233429},{"id":"https://openalex.org/C2777299769","wikidata":"https://www.wikidata.org/wiki/Q3707858","display_name":"Type (biology)","level":2,"score":0.4110153019428253},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3705425262451172},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33955660462379456},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33556878566741943},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3280487060546875},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2395494282245636},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21568256616592407},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1907556653022766},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.14147493243217468},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10349756479263306},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.06615626811981201},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1057661.1057681","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1057661.1057681","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1987067207","https://openalex.org/W2046812935","https://openalex.org/W2050045330","https://openalex.org/W2063553865","https://openalex.org/W2095821893","https://openalex.org/W2142785340","https://openalex.org/W2153981889","https://openalex.org/W6647247228"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W4306968100","https://openalex.org/W2171986175","https://openalex.org/W2089791793","https://openalex.org/W2038858740","https://openalex.org/W98108296","https://openalex.org/W2937730914"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"flat":[3,69,109],"and":[4,21,58,88],"hierarchical":[5,101,113],"approaches":[6,26],"for":[7,75,133],"generating":[8],"a":[9],"minimum-width":[10],"transistor":[11,47],"placement":[12,48,74],"of":[13,18,42,78,84,91,95,107,116,124],"CMOS":[14,37],"cells":[15,38,81,97,118],"in":[16,119],"presence":[17],"non-dual":[19],"P":[20,57],"N":[22,59],"type":[23,60],"transistors.":[24],"Our":[25],"are":[27,103,128],"the":[28,46,56,85,89,108,112,139],"first":[29],"exact":[30,141],"method":[31],"which":[32],"can":[33],"be":[34],"applied":[35],"to":[36],"with":[39],"any":[40],"types":[41],"structure.":[43],"We":[44],"formulate":[45],"problem":[49,54],"into":[50],"Boolean":[51],"Satisfiability":[52],"(SAT)":[53],"considering":[55],"transistors":[61],"individually.":[62],"The":[63],"experimental":[64],"results":[65],"show":[66],"that":[67,83,106],"our":[68,100],"approach":[70,102],"generates":[71],"smaller":[72],"width":[73,90],"29":[76],"out":[77,94],"103":[79],"dual":[80],"than":[82,105],"conventional":[86,140],"method,":[87],"only":[92],"3":[93],"147":[96],"solved":[98,129],"by":[99],"larger":[104],"approach.":[110],"Using":[111],"approach,":[114],"81%":[115],"340":[117],"an":[120],"industrial":[121],"standard-cell":[122],"library":[123],"90":[125],"nm":[126],"technology":[127],"within":[130],"one":[131],"hour":[132],"each":[134],"cell,":[135],"whereas":[136],"32%":[137],"using":[138],"method.":[142]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}