{"id":"https://openalex.org/W2075896072","doi":"https://doi.org/10.1145/1055137.1055166","title":"An efficient technology mapping algorithm targeting routing congestion under delay constraints","display_name":"An efficient technology mapping algorithm targeting routing congestion under delay constraints","publication_year":2005,"publication_date":"2005-04-03","ids":{"openalex":"https://openalex.org/W2075896072","doi":"https://doi.org/10.1145/1055137.1055166","mag":"2075896072"},"language":"en","primary_location":{"id":"doi:10.1145/1055137.1055166","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1055137.1055166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 international symposium on Physical design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029632511","display_name":"Rupesh S. Shelar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rupesh S. Shelar","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Intel Corporation, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043534115","display_name":"Prashant Saxena","orcid":"https://orcid.org/0000-0001-5071-726X"},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Prashant Saxena","raw_affiliation_strings":["Synopsys Inc., Hillsboro, OR","Synopsys Inc, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Hillsboro, OR","institution_ids":["https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys Inc, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103517539","display_name":"Xinning Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xinning Wang","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Intel Corporation, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068714995","display_name":"Sachin S. Sapatnekar","orcid":"https://orcid.org/0000-0002-5353-2364"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sachin S. Sapatnekar","raw_affiliation_strings":["University of Minnesota, Minneapolis, MN","University of Minnesota , Minneapolis, Mn"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota, Minneapolis, MN","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"University of Minnesota , Minneapolis, Mn","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.3246,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.94557823,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"137","last_page":"144"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7494539618492126},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7444390654563904},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6793027520179749},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5234674215316772},{"id":"https://openalex.org/keywords/probabilistic-logic","display_name":"Probabilistic logic","score":0.5183952450752258},{"id":"https://openalex.org/keywords/network-congestion","display_name":"Network congestion","score":0.46508166193962097},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3749402165412903},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.32776033878326416},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3228970170021057},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2727700471878052},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15741989016532898},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10898077487945557},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.08217325806617737}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7494539618492126},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7444390654563904},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6793027520179749},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5234674215316772},{"id":"https://openalex.org/C49937458","wikidata":"https://www.wikidata.org/wiki/Q2599292","display_name":"Probabilistic logic","level":2,"score":0.5183952450752258},{"id":"https://openalex.org/C195563490","wikidata":"https://www.wikidata.org/wiki/Q180368","display_name":"Network congestion","level":3,"score":0.46508166193962097},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3749402165412903},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.32776033878326416},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3228970170021057},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2727700471878052},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15741989016532898},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10898077487945557},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.08217325806617737},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1055137.1055166","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1055137.1055166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 international symposium on Physical design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.77.1450","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.77.1450","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.umn.edu/users/sachin/conf/ispd05rs.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4000000059604645,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1972047514","https://openalex.org/W2006152335","https://openalex.org/W2008011539","https://openalex.org/W2012173826","https://openalex.org/W2025516544","https://openalex.org/W2093513607","https://openalex.org/W2102502584","https://openalex.org/W2103626283","https://openalex.org/W2105616993","https://openalex.org/W2123980833","https://openalex.org/W2135117148","https://openalex.org/W2142078726","https://openalex.org/W2143250861","https://openalex.org/W2145126108","https://openalex.org/W2146664966","https://openalex.org/W2148618168","https://openalex.org/W2166011990","https://openalex.org/W2172749517","https://openalex.org/W2427843410","https://openalex.org/W3203992401"],"related_works":["https://openalex.org/W2378211422","https://openalex.org/W4321353415","https://openalex.org/W2745001401","https://openalex.org/W2130974462","https://openalex.org/W2028665553","https://openalex.org/W2086519370","https://openalex.org/W972276598","https://openalex.org/W4246352526","https://openalex.org/W4205718258","https://openalex.org/W1989674257"],"abstract_inverted_index":{"Routing":[0],"congestion":[1,23,41,48,56],"has":[2],"become":[3],"a":[4,16,30,78],"serious":[5],"concern":[6],"in":[7,34,77],"today's":[8],"VLSI":[9],"designs.":[10],"In":[11],"this":[12],"paper,":[13],"we":[14],"propose":[15],"technology":[17,81,100],"mapping":[18,101],"algorithm":[19,28,85],"that":[20,83],"minimizes":[21],"routing":[22,55],"under":[24],"delay":[25,104],"constraints.":[26,105],"The":[27],"employs":[29],"dynamic":[31],"programming":[32],"framework":[33],"the":[35,45,58,62,65,68,84,98],"matching":[36],"phase":[37],"to":[38,53,97],"generate":[39],"probabilistic":[40],"maps":[42,49],"for":[43],"all":[44],"matches.":[46],"These":[47],"are":[50],"then":[51],"utilized":[52],"minimize":[54],"during":[57],"covering,":[59],"which":[60],"preserves":[61],"delay-optimality":[63],"of":[64,70],"solution":[66],"using":[67],"notion":[69],"slack.":[71],"Experimental":[72],"results":[73],"on":[74,92],"benchmark":[75],"circuits":[76],"100":[79],"nm":[80],"show":[82],"can":[86],"improve":[87],"track":[88],"overflows":[89],"by":[90],"44%,":[91],"an":[93],"average,":[94],"as":[95],"compared":[96],"conventional":[99],"while":[102],"satisfying":[103]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-08-12T21:12:35.861297","created_date":"2025-10-10T00:00:00"}