{"id":"https://openalex.org/W2028021655","doi":"https://doi.org/10.1145/1054943.1054960","title":"SCIMA-SMP","display_name":"SCIMA-SMP","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W2028021655","doi":"https://doi.org/10.1145/1054943.1054960","mag":"2028021655"},"language":"en","primary_location":{"id":"doi:10.1145/1054943.1054960","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1054943.1054960","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085207887","display_name":"Chikafumi Takahashi","orcid":null},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Chikafumi Takahashi","raw_affiliation_strings":["University of Tsukuba","university of Tsukuba"],"affiliations":[{"raw_affiliation_string":"University of Tsukuba","institution_ids":["https://openalex.org/I146399215"]},{"raw_affiliation_string":"university of Tsukuba","institution_ids":["https://openalex.org/I146399215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103017591","display_name":"Masaaki Kondo","orcid":"https://orcid.org/0000-0002-6025-8738"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masaaki Kondo","raw_affiliation_strings":["University of Tokyo","university of Tokyo;"],"affiliations":[{"raw_affiliation_string":"University of Tokyo","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"university of Tokyo;","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020716792","display_name":"Taisuke Boku","orcid":"https://orcid.org/0000-0001-8730-2228"},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Taisuke Boku","raw_affiliation_strings":["University of Tsukuba","university of Tsukuba"],"affiliations":[{"raw_affiliation_string":"University of Tsukuba","institution_ids":["https://openalex.org/I146399215"]},{"raw_affiliation_string":"university of Tsukuba","institution_ids":["https://openalex.org/I146399215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100710410","display_name":"Daisuke Takahashi","orcid":"https://orcid.org/0000-0003-1357-5770"},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Daisuke Takahashi","raw_affiliation_strings":["University of Tsukuba","university of Tsukuba"],"affiliations":[{"raw_affiliation_string":"University of Tsukuba","institution_ids":["https://openalex.org/I146399215"]},{"raw_affiliation_string":"university of Tsukuba","institution_ids":["https://openalex.org/I146399215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090578339","display_name":"Hiroshi Nakamura","orcid":"https://orcid.org/0009-0005-6505-1903"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroshi Nakamura","raw_affiliation_strings":["University of Tokyo","university of Tokyo;"],"affiliations":[{"raw_affiliation_string":"University of Tokyo","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"university of Tokyo;","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040254066","display_name":"Mitsuhisa Sato","orcid":"https://orcid.org/0000-0003-0543-7116"},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Mitsuhisa Sato","raw_affiliation_strings":["University of Tsukuba","university of Tsukuba"],"affiliations":[{"raw_affiliation_string":"University of Tsukuba","institution_ids":["https://openalex.org/I146399215"]},{"raw_affiliation_string":"university of Tsukuba","institution_ids":["https://openalex.org/I146399215"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5085207887"],"corresponding_institution_ids":["https://openalex.org/I146399215"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12018792,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"121","last_page":"128"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8372318744659424},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.6192833185195923},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5288162231445312},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5210632681846619},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5204132795333862},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5102188587188721},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4812764525413513},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4671897888183594},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.4472157955169678},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.43981242179870605},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4318457841873169},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4310232698917389},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.4267072081565857},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.42311346530914307},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.41234827041625977},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3742639422416687},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34962382912635803},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.30693286657333374},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.24764379858970642},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.2359810769557953},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.19268110394477844},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18852579593658447}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8372318744659424},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.6192833185195923},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5288162231445312},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5210632681846619},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5204132795333862},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5102188587188721},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4812764525413513},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4671897888183594},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.4472157955169678},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.43981242179870605},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4318457841873169},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4310232698917389},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.4267072081565857},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.42311346530914307},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.41234827041625977},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3742639422416687},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34962382912635803},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.30693286657333374},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.24764379858970642},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.2359810769557953},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.19268110394477844},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18852579593658447}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1054943.1054960","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1054943.1054960","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5299999713897705,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320338075","display_name":"Core Research for Evolutional Science and Technology","ror":"https://ror.org/00097mb19"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1957395430","https://openalex.org/W1988888548","https://openalex.org/W2009291967","https://openalex.org/W2080958936","https://openalex.org/W2094332102","https://openalex.org/W2098220211","https://openalex.org/W2110896398","https://openalex.org/W2112980698","https://openalex.org/W2119042753","https://openalex.org/W2130048397","https://openalex.org/W2142033140","https://openalex.org/W2155216327","https://openalex.org/W2168878642","https://openalex.org/W2169667046"],"related_works":["https://openalex.org/W2145484885","https://openalex.org/W1959889508","https://openalex.org/W1975698617","https://openalex.org/W2047684617","https://openalex.org/W2168886965","https://openalex.org/W2041174925","https://openalex.org/W4233816696","https://openalex.org/W4389371524","https://openalex.org/W2916844530","https://openalex.org/W2021009496"],"abstract_inverted_index":{"In":[0],"this":[1,58,102],"paper,":[2],"we":[3,99],"propose":[4],"a":[5,13,38],"processor":[6,39],"architecture":[7,59,103],"with":[8,28,83],"programmable":[9],"on-chip":[10,53,124],"memory":[11,54],"for":[12,26,95],"high-performance":[14],"SMP":[15,77],"(symmetric":[16],"multi-processor)":[17],"node":[18],"named":[19],"SCIMA-SMP":[20],"(Software":[21],"Controlled":[22],"Integrated":[23],"Memory":[24],"Architecture":[25],"SMP)":[27],"the":[29,33,48,64,72,76,88,106,117,120],"intent":[30],"of":[31,119],"solving":[32],"performance":[34,89],"gap":[35],"problem":[36],"between":[37,52,123],"and":[40,55,68,75,115,125],"off-chip":[41,56,126],"memory.":[42,127],"With":[43],"special":[44],"instructions":[45],"which":[46],"enable":[47],"explicit":[49],"data":[50,65,113,121],"transfer":[51,66,114],"memory,":[57],"is":[60,79],"able":[61],"to":[62],"control":[63],"timing":[67],"its":[69],"granularity":[70,118],"by":[71,110],"application":[73],"program,":[74],"bus":[78,107],"utilized":[80],"efficiently":[81],"compared":[82],"traditional":[84],"cache-only":[85],"architecture.":[86],"Through":[87],"evaluation":[90],"based":[91],"on":[92],"clock-level":[93],"simulation":[94],"various":[96],"HPC":[97],"applications,":[98],"confirmed":[100],"that":[101],"largely":[104],"reduces":[105],"access":[108],"cycle":[109],"avoiding":[111],"redundant":[112],"controlling":[116],"movement":[122]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}