{"id":"https://openalex.org/W2025304002","doi":"https://doi.org/10.1145/1054943.1054954","title":"A study of performance impact of memory controller features in multi-processor server environment","display_name":"A study of performance impact of memory controller features in multi-processor server environment","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W2025304002","doi":"https://doi.org/10.1145/1054943.1054954","mag":"2025304002"},"language":"en","primary_location":{"id":"doi:10.1145/1054943.1054954","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1054943.1054954","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064216495","display_name":"C. Natarajan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chitra Natarajan","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corporation, Santa Clara, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064270490","display_name":"Bruce Christenson","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bruce Christenson","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corporation, Santa Clara, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020889951","display_name":"Fay\u00e9 A. Briggs","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fay\u00e9 Briggs","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corporation, Santa Clara, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.7101,"has_fulltext":false,"cited_by_count":86,"citation_normalized_percentile":{"value":0.92647777,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"80","last_page":"87"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.8141689300537109},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8021492958068848},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.7187204957008362},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6006535291671753},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5628120303153992},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5247052907943726},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.5199145674705505},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.48914673924446106},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.47705167531967163},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.46567508578300476},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46279215812683105},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.45922958850860596},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.4171029031276703},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3874017596244812},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3868711292743683},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32493287324905396},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3152359426021576},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.24822798371315002}],"concepts":[{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.8141689300537109},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8021492958068848},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.7187204957008362},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6006535291671753},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5628120303153992},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5247052907943726},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.5199145674705505},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.48914673924446106},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.47705167531967163},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.46567508578300476},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46279215812683105},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.45922958850860596},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.4171029031276703},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3874017596244812},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3868711292743683},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32493287324905396},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3152359426021576},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.24822798371315002},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1054943.1054954","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1054943.1054954","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1538592187","https://openalex.org/W1555915743","https://openalex.org/W1915361240","https://openalex.org/W2044643398","https://openalex.org/W2100335359","https://openalex.org/W2106449576","https://openalex.org/W2115172404","https://openalex.org/W2126569725","https://openalex.org/W2167233984"],"related_works":["https://openalex.org/W2019238062","https://openalex.org/W2155373950","https://openalex.org/W3008068282","https://openalex.org/W3048967625","https://openalex.org/W2138825797","https://openalex.org/W773491645","https://openalex.org/W2491097902","https://openalex.org/W101244504","https://openalex.org/W2025304002","https://openalex.org/W2047684617"],"abstract_inverted_index":{"With":[0],"the":[1,17,23,29,38,74,95,109,116],"growing":[2],"imbalance":[3],"between":[4],"processor":[5],"and":[6,12,97],"memory":[7,18,30,43,56,75,98,104,120],"performance":[8,26,39,66],"it":[9],"becomes":[10],"more":[11,13],"important":[14],"to":[15,21],"optimize":[16],"controller":[19,44,76,105],"features":[20,45],"obtain":[22],"maximum":[24],"possible":[25],"out":[27],"of":[28,37,41,81,112,118,136],"subsystem.":[31,57],"This":[32],"paper":[33],"presents":[34],"a":[35,53,87,133,142],"study":[36,123],"impact":[40],"several":[42],"in":[46,86],"multi-processor":[47],"(MP)":[48],"server":[49],"environments":[50],"that":[51,64,85,125],"use":[52],"DDR/DDR2":[54],"based":[55],"The":[58],"results":[59],"from":[60],"our":[61,82],"studies":[62,83],"show":[63],"significant":[65],"improvements":[67],"can":[68,107,138],"be":[69,139],"obtained":[70,140],"by":[71,141],"carefully":[72],"optimizing":[73],"features.":[77],"For":[78],"instance,":[79],"one":[80],"shows":[84,124],"system":[88],"with":[89],"an":[90,100],"in-order":[91],"shared":[92],"bus":[93],"connecting":[94],"CPUs":[96],"controller,":[99],"intelligent":[101],"read-to-write":[102],"switching":[103],"feature":[106],"provide":[108],"same":[110],"order":[111],"benefit":[113],"as":[114],"doubling":[115],"number":[117],"interleaved":[119],"ranks.":[121],"Another":[122],"much":[126],"lower":[127],"average":[128],"loaded":[129],"read":[130],"latency":[131],"across":[132],"wider":[134],"range":[135],"throughput":[137],"delayed":[143],"write":[144],"scheduling":[145],"feature.":[146]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":5},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":8}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}