{"id":"https://openalex.org/W2034266103","doi":"https://doi.org/10.1145/1054943.1054948","title":"Micro-architecture techniques in the intel\u00ae E8870 scalable memory controller","display_name":"Micro-architecture techniques in the intel\u00ae E8870 scalable memory controller","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W2034266103","doi":"https://doi.org/10.1145/1054943.1054948","mag":"2034266103"},"language":"en","primary_location":{"id":"doi:10.1145/1054943.1054948","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1054943.1054948","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020889951","display_name":"Fay\u00e9 A. Briggs","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fay\u00e9 Briggs","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corporation, Santa Clara, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065438530","display_name":"Suresh Chittor","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Suresh Chittor","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corporation, Santa Clara, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017178328","display_name":"Kai Cheng","orcid":"https://orcid.org/0009-0006-8221-381X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kai Cheng","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corporation, Santa Clara, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.1608,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.42392549,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"30","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8351601362228394},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7500842809677124},{"id":"https://openalex.org/keywords/chipset","display_name":"Chipset","score":0.7291920185089111},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.658165454864502},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5440948605537415},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5266777276992798},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4502531588077545},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.43014970421791077},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3928835690021515},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.3315446376800537},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.28355658054351807},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24188491702079773},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20674744248390198},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.13170567154884338},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.09338834881782532}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8351601362228394},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7500842809677124},{"id":"https://openalex.org/C73431340","wikidata":"https://www.wikidata.org/wiki/Q182656","display_name":"Chipset","level":3,"score":0.7291920185089111},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.658165454864502},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5440948605537415},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5266777276992798},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4502531588077545},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.43014970421791077},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3928835690021515},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.3315446376800537},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.28355658054351807},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24188491702079773},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20674744248390198},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.13170567154884338},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.09338834881782532},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1054943.1054948","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1054943.1054948","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2044643398","https://openalex.org/W2082225037","https://openalex.org/W2098537124","https://openalex.org/W2104674486","https://openalex.org/W2115172404"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2130320819","https://openalex.org/W2534610203","https://openalex.org/W4210611780","https://openalex.org/W4243618206","https://openalex.org/W2025304002","https://openalex.org/W2138825797","https://openalex.org/W2047684617","https://openalex.org/W2896161911","https://openalex.org/W1979830285"],"abstract_inverted_index":{"This":[0],"paper":[1,108],"describes":[2],"several":[3],"selected":[4,103],"micro-architectural":[5],"tradeoffs":[6],"and":[7,35,60,79,85],"optimizations":[8,65],"for":[9,125,128],"the":[10,15,55,69,129],"scalable":[11,26,43,113],"memory":[12,44,87,114],"controller":[13,45],"of":[14,50,71],"Intel":[16,21],"E8870":[17,22],"chipset":[18,23],"architecture.":[19],"The":[20,42,63,102],"architecture":[24],"supports":[25],"coherent":[27],"multiprocessor":[28],"systems":[29,127],"using":[30],"2":[31],"to":[32,53,90,97,112],"16":[33],"processors,":[34],"a":[36,48],"point-to-point":[37,83],"Scalability":[38],"Port":[39],"(SP)":[40],"Protocol.":[41],"micro-architecture":[46,51],"applies":[47],"number":[49],"techniques":[52,104,121],"reduce":[54],"local":[56],"&":[57],"remote":[58],"idle":[59],"loaded":[61],"latencies.":[62],"performance":[64],"were":[66],"achieved":[67],"within":[68],"constraints":[70],"maintaining":[72],"functional":[73],"correctness,":[74],"while":[75],"reducing":[76],"implementation":[77],"complexity":[78],"cost.":[80],"High":[81],"bandwidth":[82],"interconnects":[84],"distributed":[86],"are":[88],"expected":[89],"be":[91,110],"more":[92],"common":[93],"in":[94,106,117],"future":[95],"platforms":[96],"support":[98],"powerful":[99],"multi-core":[100],"processors.":[101],"discussed":[105],"this":[107],"will":[109],"applicable":[111],"controllers":[115],"needed":[116],"those":[118],"platforms.":[119,133],"These":[120],"have":[122],"been":[123],"proven":[124],"production":[126],"Itanium\u00ae":[130],"II":[131],"Processor":[132]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
