{"id":"https://openalex.org/W1990433043","doi":"https://doi.org/10.1145/1054943.1054946","title":"A low cost, multithreaded processing-in-memory system","display_name":"A low cost, multithreaded processing-in-memory system","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W1990433043","doi":"https://doi.org/10.1145/1054943.1054946","mag":"1990433043"},"language":"en","primary_location":{"id":"doi:10.1145/1054943.1054946","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1054943.1054946","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026229568","display_name":"Jay Brockman","orcid":null},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jay B. Brockman","raw_affiliation_strings":["University of Notre Dame, Notre Dame, IN","Univ of Notre Dame, Notre Dame, IN"],"affiliations":[{"raw_affiliation_string":"University of Notre Dame, Notre Dame, IN","institution_ids":["https://openalex.org/I107639228"]},{"raw_affiliation_string":"Univ of Notre Dame, Notre Dame, IN","institution_ids":["https://openalex.org/I107639228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070583152","display_name":"Shyamkumar Thoziyoor","orcid":null},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shyamkumar Thoziyoor","raw_affiliation_strings":["University of Notre Dame, Notre Dame, IN","Univ of Notre Dame, Notre Dame, IN"],"affiliations":[{"raw_affiliation_string":"University of Notre Dame, Notre Dame, IN","institution_ids":["https://openalex.org/I107639228"]},{"raw_affiliation_string":"Univ of Notre Dame, Notre Dame, IN","institution_ids":["https://openalex.org/I107639228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056450485","display_name":"Shannon K. Kuntz","orcid":null},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shannon K. Kuntz","raw_affiliation_strings":["University of Notre Dame, Notre Dame, IN","Univ of Notre Dame, Notre Dame, IN"],"affiliations":[{"raw_affiliation_string":"University of Notre Dame, Notre Dame, IN","institution_ids":["https://openalex.org/I107639228"]},{"raw_affiliation_string":"Univ of Notre Dame, Notre Dame, IN","institution_ids":["https://openalex.org/I107639228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029212199","display_name":"Peter M. Kogge","orcid":"https://orcid.org/0000-0002-3329-547X"},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter M. Kogge","raw_affiliation_strings":["University of Notre Dame, Notre Dame, IN","Univ of Notre Dame, Notre Dame, IN"],"affiliations":[{"raw_affiliation_string":"University of Notre Dame, Notre Dame, IN","institution_ids":["https://openalex.org/I107639228"]},{"raw_affiliation_string":"Univ of Notre Dame, Notre Dame, IN","institution_ids":["https://openalex.org/I107639228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5026229568"],"corresponding_institution_ids":["https://openalex.org/I107639228"],"apc_list":null,"apc_paid":null,"fwci":1.5846,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.81946816,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"16","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8379001021385193},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6845239996910095},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.631976306438446},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.6123707890510559},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5704026222229004},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4764695167541504},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4745410680770874},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.43990761041641235},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.43682193756103516},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.42827823758125305},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4191814064979553},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36342334747314453},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29458147287368774},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.24728012084960938},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24709731340408325},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.22626835107803345},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.15693992376327515}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8379001021385193},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6845239996910095},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.631976306438446},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.6123707890510559},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5704026222229004},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4764695167541504},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4745410680770874},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.43990761041641235},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.43682193756103516},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.42827823758125305},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4191814064979553},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36342334747314453},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29458147287368774},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.24728012084960938},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24709731340408325},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.22626835107803345},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.15693992376327515},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1054943.1054946","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1054943.1054946","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.58.9887","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.58.9887","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.utah.edu/wmpi2004/papers/paper-146.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W72284011","https://openalex.org/W1498916818","https://openalex.org/W1504449749","https://openalex.org/W1862469596","https://openalex.org/W1948323311","https://openalex.org/W1998040188","https://openalex.org/W2001848684","https://openalex.org/W2018761720","https://openalex.org/W2043548159","https://openalex.org/W2056893810","https://openalex.org/W2065109357","https://openalex.org/W2068306188","https://openalex.org/W2094332102","https://openalex.org/W2108507737","https://openalex.org/W2112547256","https://openalex.org/W2112590555","https://openalex.org/W2117345133","https://openalex.org/W2117500680","https://openalex.org/W2130034571","https://openalex.org/W2139952647","https://openalex.org/W2141443190","https://openalex.org/W2144430894","https://openalex.org/W2145851359","https://openalex.org/W2147301111","https://openalex.org/W2152155746","https://openalex.org/W2155066383","https://openalex.org/W2187435068"],"related_works":["https://openalex.org/W3089117407","https://openalex.org/W2023373638","https://openalex.org/W4293430534","https://openalex.org/W2342813629","https://openalex.org/W3150934690","https://openalex.org/W2335743642","https://openalex.org/W4297812927","https://openalex.org/W2800412005","https://openalex.org/W1976244802","https://openalex.org/W2083934844"],"abstract_inverted_index":{"This":[0,54],"paper":[1],"discusses":[2],"die":[3],"cost":[4,31,55,109],"vs.":[5],"performance":[6,43],"tradeoffs":[7],"for":[8,71],"a":[9,20,33,42,47,60,74,126],"PIM":[10,129],"system":[11,18],"that":[12,68],"could":[13],"serve":[14],"as":[15,97,99],"the":[16,30,81],"memory":[17],"of":[19,26,32,45,49,80,108,117],"host":[21],"processor.":[22],"For":[23],"an":[24],"increase":[25],"less":[27],"than":[28],"twice":[29],"commodity":[34],"DRAM":[35],"part,":[36],"it":[37,77],"is":[38,69],"possible":[39],"to":[40,88,100],"realize":[41],"speedup":[44],"nearly":[46],"factor":[48],"4":[50],"on":[51],"irregular":[52],"applications.":[53],"efficiency":[56],"derives":[57],"from":[58],"developing":[59],"custom":[61],"multithreaded":[62],"processor":[63,91],"architecture":[64],"and":[65,84,110,120,123],"implementation":[66],"style":[67],"well-suited":[70],"embedding":[72],"in":[73],"memory.":[75],"Specifically,":[76],"takes":[78],"advantage":[79],"low":[82],"latency":[83],"high":[85],"row":[86],"bandwidth":[87],"both":[89],"simplify":[90],"design":[92],"---":[93,96],"reducing":[94],"area":[95],"well":[98],"improve":[101],"processing":[102],"throughput.":[103],"To":[104],"support":[105],"our":[106],"claims":[107],"performance,":[111],"we":[112],"have":[113],"used":[114],"simulation,":[115],"analysis":[116],"existing":[118],"chips,":[119],"also":[121],"designed":[122],"fully":[124],"implemented":[125],"prototype":[127],"chip,":[128],"Lite.":[130]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}