{"id":"https://openalex.org/W2041266765","doi":"https://doi.org/10.1145/1053355.1053371","title":"A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool","display_name":"A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool","publication_year":2005,"publication_date":"2005-04-02","ids":{"openalex":"https://openalex.org/W2041266765","doi":"https://doi.org/10.1145/1053355.1053371","mag":"2041266765"},"language":"en","primary_location":{"id":"doi:10.1145/1053355.1053371","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1053355.1053371","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 international workshop on System level interconnect prediction","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110958951","display_name":"Young-Su Kwon","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Young-Su Kwon","raw_affiliation_strings":["Massachusetts Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016017965","display_name":"Payam Lajevardi","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Payam Lajevardi","raw_affiliation_strings":["Massachusetts Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084128470","display_name":"Anantha P. Chandrakasan","orcid":"https://orcid.org/0000-0002-5977-2748"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anantha P. Chandrakasan","raw_affiliation_strings":["Massachusetts Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030455193","display_name":"Frank Honor\u00e9","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Frank Honor\u00e9","raw_affiliation_strings":["Massachusetts Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025791255","display_name":"Donald E. Troxel","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Donald E. Troxel","raw_affiliation_strings":["Massachusetts Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5110958951"],"corresponding_institution_ids":["https://openalex.org/I63966007"],"apc_list":null,"apc_paid":null,"fwci":1.0883,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.79005175,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"65","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.900428056716919},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7517585158348083},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7515829801559448},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6863977313041687},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6322357654571533},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5519489645957947},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4290284514427185},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4109785854816437},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3391185402870178},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32126927375793457},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1043948233127594}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.900428056716919},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7517585158348083},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7515829801559448},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6863977313041687},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6322357654571533},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5519489645957947},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4290284514427185},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4109785854816437},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3391185402870178},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32126927375793457},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1043948233127594},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1053355.1053371","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1053355.1053371","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 international workshop on System level interconnect prediction","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.507.8591","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.507.8591","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www-mtl.mit.edu/researchgroups/icsystems/pubs/conferences/2005/kwon_slip2005_paper.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1485786366","https://openalex.org/W1592472700","https://openalex.org/W1991530123","https://openalex.org/W2005226599","https://openalex.org/W2014007884","https://openalex.org/W2028954821","https://openalex.org/W2056883404","https://openalex.org/W2120149280","https://openalex.org/W2125469204","https://openalex.org/W2132942644","https://openalex.org/W2139637699","https://openalex.org/W2146185334","https://openalex.org/W2147317258","https://openalex.org/W2152446494","https://openalex.org/W2165792244","https://openalex.org/W2170550019"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W2387264083","https://openalex.org/W2604877941","https://openalex.org/W3146360095","https://openalex.org/W2390885485","https://openalex.org/W2184011203","https://openalex.org/W1967468490","https://openalex.org/W4312121077"],"abstract_inverted_index":{"The":[0,72,142],"interconnection":[1,42],"architecture":[2],"of":[3,10,14,99,108,119,139,157],"FPGAs":[4,15],"such":[5],"as":[6],"switches":[7],"dominates":[8],"performance":[9],"FPGAs.":[11],"Three-dimensional":[12],"integration":[13],"overcomes":[16],"interconnect":[17],"limitations":[18],"by":[19,103,112],"allowing":[20],"instances":[21],"to":[22,27,80],"be":[23,28],"located":[24],"and":[25,40,90,122,128,166],"signals":[26],"routed":[29,123],"in":[30,44,57],"3-D":[31,45,65,82,92,126,134,144],"space.":[32],"Wire":[33],"resource":[34,75,146],"prediction":[35,76,147],"is":[36,78],"important":[37],"for":[38,63,132,136,160],"fast":[39],"accurate":[41],"planning":[43],"FPGA.":[46],"In":[47],"this":[48],"paper,":[49],"we":[50],"extend":[51],"the":[52,97,100,105,113,120,150],"existing":[53],"analytic":[54,115],"model":[55,77,102,148],"shown":[56],"[13]":[58],"with":[59,117,154],"a":[60,85,137],"new":[61],"parameter":[62],"our":[64,81,91,133],"FPGA":[66,83,135],"which":[67],"has":[68],"cluster-based":[69],"logic":[70],"blocks.":[71],"proposed":[73],"wire":[74,145],"applied":[79],"using":[84,125],"Xilinx":[86],"Virtex2":[87],"slice":[88],"[18]":[89],"routing":[93,129],"architecture.":[94],"We":[95],"validate":[96],"effectiveness":[98],"extended":[101,114,143],"comparing":[104],"required":[106,151],"number":[107,138],"channel":[109,152],"wires":[110],"predicted":[111],"equation":[116],"that":[118],"placed":[121],"results":[124],"placement":[127],"algorithm":[130],"designed":[131],"benchmark":[140],"circuits.":[141],"predicts":[149],"capacity":[153],"an":[155],"average":[156],"11.1%":[158],"error":[159],"17":[161],"large":[162],"circuits":[163],"from":[164],"LGSynth93":[165],"ISPD2001":[167],"Verilog":[168],"benchmarks.":[169]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
