{"id":"https://openalex.org/W2086638905","doi":"https://doi.org/10.1145/1053355.1053364","title":"Dealing with interconnect process variations","display_name":"Dealing with interconnect process variations","publication_year":2005,"publication_date":"2005-04-02","ids":{"openalex":"https://openalex.org/W2086638905","doi":"https://doi.org/10.1145/1053355.1053364","mag":"2086638905"},"language":"en","primary_location":{"id":"doi:10.1145/1053355.1053364","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1053355.1053364","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 international workshop on System level interconnect prediction","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113645794","display_name":"N.S. Nagaraj","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"N. S. Nagaraj","raw_affiliation_strings":["Texas Instruments Inc., Dallas TX","texas Instruments Incorporated (Dallas, TX)"],"affiliations":[{"raw_affiliation_string":"Texas Instruments Inc., Dallas TX","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"texas Instruments Incorporated (Dallas, TX)","institution_ids":["https://openalex.org/I74760111"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5113645794"],"corresponding_institution_ids":["https://openalex.org/I74760111"],"apc_list":null,"apc_paid":null,"fwci":0.7114,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.7394646,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"39","last_page":"39"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7661428451538086},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.6229228973388672},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5650922656059265},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.5167676210403442},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.48070675134658813},{"id":"https://openalex.org/keywords/chemical-mechanical-planarization","display_name":"Chemical-mechanical planarization","score":0.44729477167129517},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.44420239329338074},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.42137208580970764},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.39798504114151},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3110545873641968},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3071059584617615},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25922271609306335},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.2417018711566925},{"id":"https://openalex.org/keywords/polishing","display_name":"Polishing","score":0.2322733998298645},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10632893443107605},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09167259931564331}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7661428451538086},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.6229228973388672},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5650922656059265},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.5167676210403442},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.48070675134658813},{"id":"https://openalex.org/C180088628","wikidata":"https://www.wikidata.org/wiki/Q1069404","display_name":"Chemical-mechanical planarization","level":3,"score":0.44729477167129517},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.44420239329338074},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.42137208580970764},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.39798504114151},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3110545873641968},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3071059584617615},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25922271609306335},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2417018711566925},{"id":"https://openalex.org/C138113353","wikidata":"https://www.wikidata.org/wiki/Q611639","display_name":"Polishing","level":2,"score":0.2322733998298645},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10632893443107605},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09167259931564331},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1053355.1053364","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1053355.1053364","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 international workshop on System level interconnect prediction","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2350003910","https://openalex.org/W2489206082","https://openalex.org/W1495339469","https://openalex.org/W1999768459","https://openalex.org/W2130148791","https://openalex.org/W2155451298","https://openalex.org/W2163264803","https://openalex.org/W74903192","https://openalex.org/W4226027024","https://openalex.org/W1520075683"],"abstract_inverted_index":{"Historically,":[0],"transistor":[1],"process":[2,29,49,79,87],"variations":[3,30,65,69,80,88,106],"have":[4],"been":[5],"studied":[6],"in":[7,70],"great":[8],"detail.":[9],"As":[10],"interconnect":[11,28,48,86],"becomes":[12],"a":[13,38],"significant":[14],"portion":[15],"of":[16,27,41,45,84],"circuit":[17,92,112],"performance,":[18],"signal":[19],"integrity,":[20],"power":[21],"integrity":[22],"and":[23,43,57,66,77,98,107],"chip":[24],"reliability,":[25],"study":[26],"has":[31],"gained":[32],"increased":[33],"importance.":[34],"This":[35],"paper":[36],"provides":[37],"comprehensive":[39],"overview":[40],"types":[42],"sources":[44],"all":[46],"aspects":[47],"variations,":[50],"including":[51],"VIA,":[52],"contact,":[53],"metal,":[54],"dielectric":[55],"barriers":[56],"low-k":[58],"dielectrics.":[59],"Chemical":[60],"Mechanical":[61],"Polishing":[62],"(CMP)":[63],"induced":[64,68],"etch":[67],"metal":[71],"topography":[72],"are":[73,81,100,114],"covered.":[74,115],"Both":[75],"systematic":[76],"random":[78],"discussed.":[82,101],"Impact":[83],"these":[85],"on":[89,110],"RC":[90],"delay,":[91,93],"crosstalk":[94],"noise,":[95],"voltage":[96],"drop":[97],"EM":[99],"Methods":[102],"to":[103],"determine":[104],"intra-level/inter-level":[105],"their":[108],"impact":[109],"potential":[111],"hazards":[113]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
