{"id":"https://openalex.org/W2045159173","doi":"https://doi.org/10.1145/1046192.1046260","title":"An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only)","display_name":"An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only)","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W2045159173","doi":"https://doi.org/10.1145/1046192.1046260","mag":"2045159173"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046260","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046260","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088398746","display_name":"Sven Heithecker","orcid":null},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Sven Heithecker","raw_affiliation_strings":["Technical University of Braunschweig, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Technical University of Braunschweig, Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075507551","display_name":"Rolf Ernst","orcid":"https://orcid.org/0000-0003-2414-9566"},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rolf Ernst","raw_affiliation_strings":["Technical University of Braunschweig, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Technical University of Braunschweig, Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5088398746"],"corresponding_institution_ids":["https://openalex.org/I94509681"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1582489,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"277","last_page":"277"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9901000261306763,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8370632529258728},{"id":"https://openalex.org/keywords/quality-of-service","display_name":"Quality of service","score":0.6799848079681396},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6577383279800415},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6344457864761353},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6194843053817749},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5493199825286865},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.5425077676773071},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.517275869846344},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5120015740394592},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.49965739250183105},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4982903003692627},{"id":"https://openalex.org/keywords/video-decoder","display_name":"Video decoder","score":0.4472261667251587},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4175627827644348},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3491109311580658},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2835831344127655},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.23759129643440247},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23566895723342896},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.12791162729263306},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08225828409194946}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8370632529258728},{"id":"https://openalex.org/C5119721","wikidata":"https://www.wikidata.org/wiki/Q220501","display_name":"Quality of service","level":2,"score":0.6799848079681396},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6577383279800415},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6344457864761353},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6194843053817749},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5493199825286865},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.5425077676773071},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.517275869846344},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5120015740394592},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.49965739250183105},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4982903003692627},{"id":"https://openalex.org/C2776580754","wikidata":"https://www.wikidata.org/wiki/Q25098614","display_name":"Video decoder","level":3,"score":0.4472261667251587},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4175627827644348},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3491109311580658},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2835831344127655},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.23759129643440247},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23566895723342896},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.12791162729263306},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08225828409194946},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1046192.1046260","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046260","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2547220881","https://openalex.org/W1603816627","https://openalex.org/W2532617734","https://openalex.org/W2082939521","https://openalex.org/W2056138949","https://openalex.org/W2132401245","https://openalex.org/W3089341786","https://openalex.org/W2543262377","https://openalex.org/W2557931434","https://openalex.org/W2023569851"],"abstract_inverted_index":{"Today":[0],"high-end":[1,138],"video":[2,71,79,139],"and":[3,73,98,116],"multimedia":[4],"processing":[5],"applications":[6],"require":[7],"huge":[8],"amounts":[9],"of":[10,17,40,58,93,144],"memory.":[11],"For":[12],"cost":[13],"reasons,":[14],"the":[15,113,125,142],"usage":[16],"conventional":[18],"dynamic":[19],"RAM":[20],"(SDRAM)":[21],"is":[22,28,43],"preferred.":[23],"However,":[24],"SDRAM":[25],"access":[26,35],"optimization":[27],"a":[29,51,91],"complex":[30],"task,":[31],"especially":[32],"if":[33],"multi-stream":[34,52],"with":[36,134],"different":[37],"QoS":[38,85],"(Quality":[39],"Service)":[41],"requirements":[42,61,86],"involved.":[44],"At":[45],"SIPS":[46],"2003":[47],"conference,":[48],"we":[49],"presented":[50],"DDR-SDRAM":[53],"controller":[54,122,126],"IP":[55],"covering":[56],"combinations":[57],"low":[59],"latency":[60],"for":[62,69,78,129],"processor":[63],"cache":[64],"access,":[65],"hard":[66,74],"real-time":[67,75],"constraints":[68],"periodic":[70],"signals":[72],"bursty":[76],"accesses":[77],"coprocessors.":[80],"To":[81],"handle":[82],"these":[83],"contradictory":[84],"at":[87],"high":[88],"system":[89],"performance,":[90],"combination":[92],"an":[94,106],"2-stage":[95],"scheduling":[96],"algorithm":[97],"static":[99],"priorities":[100],"was":[101],"used.":[102],"This":[103],"poster":[104],"describes":[105],"additional":[107],"flow":[108],"control":[109],"which":[110],"greatly":[111],"enhances":[112],"overall":[114],"performance":[115],"controlability.":[117],"The":[118],"efficient":[119],"but":[120],"simple":[121],"design":[123],"makes":[124],"well":[127],"suited":[128],"FPGA":[130,136],"based":[131,137],"designs.":[132],"Experiments":[133],"our":[135],"platform":[140],"demonstrate":[141],"superiority":[143],"this":[145],"architecture.":[146]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}