{"id":"https://openalex.org/W2010564699","doi":"https://doi.org/10.1145/1046192.1046253","title":"Dynamic reconfiguration in FPGA-based SoC designs (abstract only)","display_name":"Dynamic reconfiguration in FPGA-based SoC designs (abstract only)","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W2010564699","doi":"https://doi.org/10.1145/1046192.1046253","mag":"2010564699"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046253","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046253","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072165834","display_name":"Roman Bartosi\u0144ski","orcid":null},"institutions":[{"id":"https://openalex.org/I202391551","display_name":"Czech Academy of Sciences","ror":"https://ror.org/053avzc18","country_code":"CZ","type":"funder","lineage":["https://openalex.org/I202391551"]}],"countries":["CZ"],"is_corresponding":true,"raw_author_name":"Roman Bartosinski","raw_affiliation_strings":["Czech Academy of Sciences, Czech Republic","Czech Academy of Sciences, Czech Republic#TAB#"],"affiliations":[{"raw_affiliation_string":"Czech Academy of Sciences, Czech Republic","institution_ids":["https://openalex.org/I202391551"]},{"raw_affiliation_string":"Czech Academy of Sciences, Czech Republic#TAB#","institution_ids":["https://openalex.org/I202391551"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000486088","display_name":"Martin Dan\u011bk","orcid":null},"institutions":[{"id":"https://openalex.org/I202391551","display_name":"Czech Academy of Sciences","ror":"https://ror.org/053avzc18","country_code":"CZ","type":"funder","lineage":["https://openalex.org/I202391551"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Martin Dan\u011bk","raw_affiliation_strings":["Czech Academy of Sciences, Czech Republic","Czech Academy of Sciences, Czech Republic#TAB#"],"affiliations":[{"raw_affiliation_string":"Czech Academy of Sciences, Czech Republic","institution_ids":["https://openalex.org/I202391551"]},{"raw_affiliation_string":"Czech Academy of Sciences, Czech Republic#TAB#","institution_ids":["https://openalex.org/I202391551"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032605421","display_name":"Petr Honz\u00edk","orcid":null},"institutions":[{"id":"https://openalex.org/I202391551","display_name":"Czech Academy of Sciences","ror":"https://ror.org/053avzc18","country_code":"CZ","type":"funder","lineage":["https://openalex.org/I202391551"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Petr Honz\u00edk","raw_affiliation_strings":["Czech Academy of Sciences, Czech Republic","Czech Academy of Sciences, Czech Republic#TAB#"],"affiliations":[{"raw_affiliation_string":"Czech Academy of Sciences, Czech Republic","institution_ids":["https://openalex.org/I202391551"]},{"raw_affiliation_string":"Czech Academy of Sciences, Czech Republic#TAB#","institution_ids":["https://openalex.org/I202391551"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049286127","display_name":"Rudolf Matou\u0161ek","orcid":null},"institutions":[{"id":"https://openalex.org/I202391551","display_name":"Czech Academy of Sciences","ror":"https://ror.org/053avzc18","country_code":"CZ","type":"funder","lineage":["https://openalex.org/I202391551"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Rudolf Matou\u0161ek","raw_affiliation_strings":["Czech Academy of Sciences, Czech Republic","Czech Academy of Sciences, Czech Republic#TAB#"],"affiliations":[{"raw_affiliation_string":"Czech Academy of Sciences, Czech Republic","institution_ids":["https://openalex.org/I202391551"]},{"raw_affiliation_string":"Czech Academy of Sciences, Czech Republic#TAB#","institution_ids":["https://openalex.org/I202391551"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5072165834"],"corresponding_institution_ids":["https://openalex.org/I202391551"],"apc_list":null,"apc_paid":null,"fwci":1.0312,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.77646684,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"274","last_page":"274"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.9341073036193848},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8515647649765015},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7603157758712769},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7071731090545654},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.6223464012145996},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4629081189632416},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4529031217098236},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4483814537525177},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.439652681350708},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.43469470739364624},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3735220432281494},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3616626262664795}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.9341073036193848},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8515647649765015},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7603157758712769},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7071731090545654},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.6223464012145996},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4629081189632416},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4529031217098236},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4483814537525177},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.439652681350708},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.43469470739364624},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3735220432281494},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3616626262664795},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1046192.1046253","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046253","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2204754129","https://openalex.org/W4322751528","https://openalex.org/W2759209791","https://openalex.org/W2274261625","https://openalex.org/W2543970970","https://openalex.org/W2340647897","https://openalex.org/W2034458695","https://openalex.org/W1569711686","https://openalex.org/W1541284233","https://openalex.org/W2129154773"],"abstract_inverted_index":{"This":[0],"paper":[1],"discusses":[2],"architectural":[3],"issues":[4],"arising":[5],"from":[6],"the":[7,59,62,75,78,84],"use":[8,16],"of":[9,17,61,94],"dynamic":[10,18],"reconfiguration":[11,19],"and":[12,22,83,99],"shows":[13],"a":[14,24,37,44],"possible":[15],"to":[20,48],"extend":[21],"accelerate":[23],"computation":[25],"performed":[26],"in":[27,53,92],"system-on-a-chip":[28],"designs":[29],"with":[30,32],"microprocessors":[31],"fixed":[33],"instruction":[34],"sets.":[35],"Further":[36],"sample":[38],"application":[39],"is":[40,90],"discussed":[41],"that":[42],"uses":[43],"dynamically":[45,70],"reconfigurable":[46,71],"FPGA":[47],"implement":[49],"different":[50],"floating-point":[51],"calculations":[52],"hardware,":[54],"reconfigured":[55],"as":[56],"required":[57],"by":[58],"execution":[60],"user":[63],"code.":[64],"The":[65],"implementation":[66],"data":[67],"for":[68],"two":[69],"platforms":[72],"available":[73],"on":[74],"market":[76],"-":[77,89],"Xilinx":[79],"Virtex2":[80],"family":[81,87],"FPGAs":[82,88],"Atmel":[85],"FPSLIC":[86],"compared":[91],"terms":[93],"resource":[95],"requirements,":[96],"operating":[97],"frequency,":[98],"power":[100],"consumption.":[101]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
