{"id":"https://openalex.org/W2067098602","doi":"https://doi.org/10.1145/1046192.1046249","title":"Dual-Vt FPGA design for leakage power reduction (abstract only)","display_name":"Dual-Vt FPGA design for leakage power reduction (abstract only)","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W2067098602","doi":"https://doi.org/10.1145/1046192.1046249","mag":"2067098602"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046249","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046249","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081266273","display_name":"Akhilesh Kumar","orcid":"https://orcid.org/0000-0002-0141-6388"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Akhilesh Kumar","raw_affiliation_strings":["University of Waterloo, Waterloo, Ontario","University of Waterloo, Waterloo, Ontario#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario#TAB#","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112829693","display_name":"Mohab Anis","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mohab Anis","raw_affiliation_strings":["University of Waterloo, Waterloo, Ontario","University of Waterloo, Waterloo, Ontario#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario#TAB#","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5081266273"],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":0.3557,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.65286404,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"272","last_page":"272"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7623637914657593},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.6342592835426331},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5811737775802612},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.5750770568847656},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5645195841789246},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.535979688167572},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5221403241157532},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.5130845308303833},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5086420774459839},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.49053043127059937},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.4868258833885193},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47156664729118347},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.45155441761016846},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.44930651783943176},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4428216814994812},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.42650097608566284},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4154221713542938},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37258458137512207},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30003711581230164},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2774850130081177},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.18886160850524902},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13428732752799988}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7623637914657593},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.6342592835426331},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5811737775802612},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.5750770568847656},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5645195841789246},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.535979688167572},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5221403241157532},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.5130845308303833},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5086420774459839},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.49053043127059937},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.4868258833885193},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47156664729118347},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.45155441761016846},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.44930651783943176},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4428216814994812},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.42650097608566284},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4154221713542938},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37258458137512207},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30003711581230164},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2774850130081177},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.18886160850524902},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13428732752799988},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1046192.1046249","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046249","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2135636985","https://openalex.org/W3023652529","https://openalex.org/W2139569078","https://openalex.org/W4252227487","https://openalex.org/W2134262422","https://openalex.org/W2141429499","https://openalex.org/W4248303983","https://openalex.org/W4252906329","https://openalex.org/W2151927748","https://openalex.org/W2171679639"],"abstract_inverted_index":{"Leakage":[0],"power":[1,7,34,59],"has":[2],"been":[3],"overshadowed":[4],"by":[5],"dynamic":[6],"minimization":[8],"techniques":[9],"in":[10,17,113,177],"FPGAs,":[11],"and":[12,79,129,171,180],"is":[13,39],"a":[14,23,95,144,178],"growing":[15],"concern":[16],"programmable":[18],"logic.":[19],"This":[20,90],"paper":[21],"proposes":[22],"dual":[24,96,149,197],"threshold":[25,44,81,97,120,150,198],"voltage":[26,45,82,98,151,199],"implementation":[27,99],"of":[28,54,77,109,127,153,166,169,173,189],"the":[29,47,51,55,67,75,101,110,114,160,164,167,181,187,196],"FPGA":[30,56,102,115,154],"architecture":[31],"for":[32,41,57,100,133,195],"leakage":[33,58,125,182,193],"reduction.":[35,60],"A":[36],"CAD":[37,62,91,141],"flow":[38,63,92,142],"developed":[40],"assigning":[42],"high":[43,78,119,170],"to":[46,74,94,131],"logic":[48,52,68,83,87,111,175],"elements":[49,84,112,176],"within":[50],"blocks":[53,69],"The":[61,139],"ensures":[64],"that":[65,85,106],"all":[66],"remain":[70],"identical":[71],"with":[72],"respect":[73],"number":[76,168,172],"low":[80],"each":[86],"block":[88],"contains.":[89],"leads":[93],"architecture.":[103],"Results":[104],"indicate":[105],"over":[107],"95%":[108],"can":[116,136,155],"be":[117,137,156],"assigned":[118],"voltage.":[121],"On":[122],"an":[123],"average":[124],"savings":[126,194],"60%":[128],"up":[130],"70%":[132],"some":[134],"benchmarks":[135],"achieved.":[138],"proposed":[140],"forms":[143],"basis":[145],"on":[146,192],"which":[147],"other":[148],"implementations":[152],"evaluated.":[157],"We":[158,184],"investigate":[159,186],"design":[161],"trade-offs":[162],"between":[163],"ratio":[165],"low-Vt":[174],"cluster":[179,190],"savings.":[183],"also":[185],"impact":[188],"size":[191],"implementation.":[200]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
