{"id":"https://openalex.org/W2055834800","doi":"https://doi.org/10.1145/1046192.1046243","title":"Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only)","display_name":"Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only)","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W2055834800","doi":"https://doi.org/10.1145/1046192.1046243","mag":"2055834800"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046243","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046243","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069865058","display_name":"Mehrdad Najibi","orcid":null},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Mehrdad Najibi","raw_affiliation_strings":["Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010366170","display_name":"Kamran Saleh","orcid":null},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Kamran Saleh","raw_affiliation_strings":["Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102929684","display_name":"Mohsen Naderi","orcid":"https://orcid.org/0009-0009-7484-0735"},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mohsen Naderi","raw_affiliation_strings":["Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085021768","display_name":"Hossein Pedram","orcid":"https://orcid.org/0000-0002-2331-0568"},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Hossein Pedram","raw_affiliation_strings":["Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047589127","display_name":"Sedighi Mehdi","orcid":null},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mehdi Sedighi","raw_affiliation_strings":["Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5069865058"],"corresponding_institution_ids":["https://openalex.org/I158248296"],"apc_list":null,"apc_paid":null,"fwci":0.96711955,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.78366653,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"269","last_page":"269"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8899675607681274},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7232550382614136},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6928703188896179},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5460515022277832},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5111640095710754},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4050866961479187},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39088767766952515},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3277769088745117},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12117436528205872},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12106272578239441},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11879301071166992},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09428834915161133},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.07123488187789917},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.04440629482269287}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8899675607681274},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7232550382614136},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6928703188896179},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5460515022277832},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5111640095710754},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4050866961479187},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39088767766952515},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3277769088745117},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12117436528205872},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12106272578239441},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11879301071166992},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09428834915161133},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.07123488187789917},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.04440629482269287}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1046192.1046243","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046243","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2063349212","https://openalex.org/W2533996814","https://openalex.org/W2912823933","https://openalex.org/W2005635888","https://openalex.org/W2111489015","https://openalex.org/W2549524842","https://openalex.org/W2764508460","https://openalex.org/W2811116664","https://openalex.org/W2050447126","https://openalex.org/W4241462776"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,35,70,75,124,129],"methodology":[4],"for":[5,22],"prototyping":[6],"Globally":[7],"Asynchronous":[8],"Locally":[9],"Synchronous":[10],"(GALS)":[11],"circuits":[12,25,57],"on":[13,38],"synchronous":[14,126],"commercial":[15],"FPGAs.":[16],"A":[17],"library":[18,43],"of":[19,55,88,112,140],"required":[20],"elements":[21],"implementing":[23],"GALS":[24,36,71,83,136],"is":[26,115,120,132],"proposed":[27],"and":[28,47,49,58,61,93,138],"general":[29],"design":[30],"considerations":[31],"to":[32,100,134,144],"successfully":[33],"implement":[34],"circuit":[37,90,114,127],"FPGA":[39],"are":[40,63],"discussed.":[41],"The":[42,78],"includes":[44],"clock":[45],"generators":[46],"arbiters,":[48],"different":[50,103,148],"port":[51],"controllers.":[52],"Different":[53],"implementations":[54],"these":[56],"their":[59],"advantages":[60],"disadvantages":[62],"explored.":[64],"At":[65],"the":[66,82,86,89,95,107,110,113],"end":[67],"we":[68],"present":[69],"Reed-Solomon":[72],"decoder":[73],"as":[74],"practical":[76],"example.":[77],"results":[79],"show":[80],"that":[81,123],"approach":[84],"improves":[85],"performance":[87],"by":[91,98,117],"11%":[92],"reduces":[94],"power":[96],"consumption":[97],"18.7%":[99],"19.6%":[101],"considering":[102,122],"error":[104],"rates.":[105],"On":[106],"other":[108],"hand,":[109],"area":[111],"increased":[116],"51%":[118],"which":[119],"acceptable":[121],"pure":[125],"including":[128],"central":[130],"controller":[131,146],"decomposed":[133],"generate":[135],"system":[137],"29%":[139],"this":[141,156],"overhead":[142,157],"belongs":[143],"distributing":[145],"in":[147],"modules.":[149],"Deploying":[150],"better":[151],"decomposition":[152],"methods":[153],"can":[154],"reduce":[155],"substantially.":[158]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}