{"id":"https://openalex.org/W1963611032","doi":"https://doi.org/10.1145/1046192.1046237","title":"A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only)","display_name":"A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only)","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W1963611032","doi":"https://doi.org/10.1145/1046192.1046237","mag":"1963611032"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046237","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046237","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021823528","display_name":"Hossam Hassan","orcid":"https://orcid.org/0000-0003-3932-9009"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"H. Hassan","raw_affiliation_strings":["University of Waterloo, Waterloo, Ontario","University of Waterloo, Waterloo, Ontario#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario#TAB#","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112829693","display_name":"Mohab Anis","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Anis","raw_affiliation_strings":["University of Waterloo, Waterloo, Ontario","University of Waterloo, Waterloo, Ontario#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario#TAB#","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111957282","display_name":"M. Elmasry","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Elmasry","raw_affiliation_strings":["University of Waterloo, Waterloo, Ontario","University of Waterloo, Waterloo, Ontario#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"University of Waterloo, Waterloo, Ontario#TAB#","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5021823528"],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.09565796,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"267","last_page":"267"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8232879042625427},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.7332000732421875},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6485685110092163},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5967572331428528},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5329105854034424},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.5294002294540405},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.4699666202068329},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.45227864384651184},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.45030343532562256},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.41958385705947876},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3202478289604187},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2520054578781128},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24296557903289795},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.14704766869544983},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09203043580055237},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.06507742404937744}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8232879042625427},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.7332000732421875},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6485685110092163},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5967572331428528},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5329105854034424},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.5294002294540405},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.4699666202068329},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.45227864384651184},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.45030343532562256},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.41958385705947876},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3202478289604187},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2520054578781128},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24296557903289795},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.14704766869544983},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09203043580055237},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.06507742404937744},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1046192.1046237","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046237","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2900067469","https://openalex.org/W2130342263","https://openalex.org/W2968511773","https://openalex.org/W2048043124","https://openalex.org/W2128559064","https://openalex.org/W2316140901","https://openalex.org/W3012528295","https://openalex.org/W2091720925","https://openalex.org/W1535054023","https://openalex.org/W1605920217"],"abstract_inverted_index":{"FPGAs":[0,15,41],"are":[1],"witnessing":[2],"a":[3,24,34,68,84,133],"big":[4,25],"increase":[5,26,49],"in":[6,27,30,42,50,62,77],"their":[7,125],"applications,":[8],"especially":[9],"with":[10,23,132],"the":[11,38,48,51,58,97],"introduction":[12],"of":[13,40,53,145],"state-of-the-art":[14],"using":[16],"nanometer":[17],"technologies.":[18],"This":[19],"has":[20],"been":[21],"accompanied":[22],"power":[28,55,60,75,143],"dissipation":[29,56,61,76],"FPGAs,":[31],"which":[32],"forms":[33],"road":[35],"block":[36],"to":[37,57,72,103,114],"integration":[39],"several":[43],"hand-held":[44],"applications.":[45],"Motivated":[46],"by":[47],"percentage":[52],"leakage":[54,74],"total":[59],"modern":[63],"technologies,":[64],"this":[65],"work":[66],"presents":[67],"complete":[69],"CAD":[70],"flow":[71,93,99,129],"mitigate":[73],"FPGAs.":[78],"The":[79,92,128],"algorithm":[80],"is":[81,94,130],"based":[82,95],"on":[83,96],"FPGA":[85],"architecture":[86],"that":[87,109,118],"employs":[88],"multi-threshold":[89],"CMOS":[90,134],"technology.":[91],"VPR":[98],"and":[100,105,139],"it":[101],"aims":[102],"pack":[104],"place":[106],"logic":[107],"blocks":[108],"exhibit":[110],"similar":[111],"idleness":[112],"close":[113],"each":[115],"other":[116],"so":[117],"they":[119],"can":[120],"be":[121],"turned":[122],"off":[123],"during":[124],"idle":[126],"time.":[127],"tested":[131],"0.13":[135],"m":[136],"dual-vth":[137],"technology":[138],"achieved":[140],"an":[141],"average":[142],"saving":[144],"22%.":[146]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
