{"id":"https://openalex.org/W2008464309","doi":"https://doi.org/10.1145/1046192.1046233","title":"Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)","display_name":"Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W2008464309","doi":"https://doi.org/10.1145/1046192.1046233","mag":"2008464309"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046233","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046233","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080892695","display_name":"E. Syam Sundar Reddy","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"E. Syam Sundar Reddy","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055837802","display_name":"Vikram Chandrasekhar","orcid":"https://orcid.org/0000-0002-3890-4895"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vikram Chandrasekhar","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084744415","display_name":"M. Sashikanth","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. Sashikanth","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010004459","display_name":"V. Kamakoti","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V. Kamakoti","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101919131","display_name":"Vijaykrishnan Narayanan","orcid":"https://orcid.org/0000-0001-6266-6068"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vijaykrishnan Narayanan","raw_affiliation_strings":["Pennsylvania State University, University Park, PA","PENNSYLVANIA STATE UNIVERSITY, UNIVERSITY PARK, PA"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University, University Park, PA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"PENNSYLVANIA STATE UNIVERSITY, UNIVERSITY PARK, PA","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5080892695"],"corresponding_institution_ids":["https://openalex.org/I24676775"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12574405,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"265","last_page":"265"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.927911639213562},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7299799919128418},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7101660370826721},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5926765203475952},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5694053769111633},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5424495339393616},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5117964148521423},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.47986167669296265},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44248145818710327},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3305889964103699},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2783058285713196},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15311312675476074},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11804121732711792},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09571406245231628}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.927911639213562},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7299799919128418},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7101660370826721},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5926765203475952},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5694053769111633},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5424495339393616},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5117964148521423},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.47986167669296265},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44248145818710327},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3305889964103699},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2783058285713196},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15311312675476074},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11804121732711792},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09571406245231628},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1046192.1046233","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046233","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,34,39],"new":[4],"CLB":[5],"architecture":[6,53],"for":[7,75,103,137],"FPGAs":[8],"and":[9,12,20,115],"associated":[10],"testing":[11,79],"reconfiguration":[13],"techniques":[14],"that":[15,54,86,99],"detect":[16],"single":[17,35,129],"routing/interconnect":[18],"errors":[19,85,131],"correct":[21,157],"them":[22],"using":[23],"partial":[24],"reconfiguration.":[25,76],"The":[26,59,77],"results":[27],"of":[28,50,90,108,112,118,140,149],"error":[29,60,104],"detection":[30,105],"are":[31,44],"propagated":[32],"to":[33,46,56,153,156],"output":[36],"port":[37],"by":[38,63],"chain-like":[40],"shift":[41],"register,":[42],"which":[43],"used":[45],"reduce":[47],"the":[48,51,66,73,88,91,100,110,116,122,138,150,158],"segment":[49,69],"routing":[52,84],"has":[55],"be":[57,154],"reconfigured.":[58],"is":[61,97,106],"corrected":[62],"partially":[64],"reconfiguring":[65],"above":[67],"minimal":[68],"alone,":[70],"thereby":[71],"reducing":[72],"time":[74,101],"proposed":[78],"technique":[80,126,144],"detects":[81],"all":[82,128],"possible":[83],"affects":[87],"logic":[89,119],"circuit,":[92],"including":[93],"bridging":[94],"faults.":[95],"It":[96],"noteworthy":[98],"required":[102,145],"independent":[107],"both":[109],"number":[111,117],"switch":[113,151],"matrices":[114,152],"blocks":[120],"in":[121,132],"FPGA.":[123],"Empirically,":[124],"our":[125,142],"detected":[127],"interconnect":[130],"benchmark":[133],"circuits.":[134],"In":[135],"addition,":[136],"majority":[139],"errors,":[141],"correction":[143],"less":[146],"than":[147],"10%":[148],"reconfigured":[155],"errors.":[159]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
