{"id":"https://openalex.org/W2111427553","doi":"https://doi.org/10.1145/1046192.1046220","title":"Design, layout and verification of an FPGA using automated tools","display_name":"Design, layout and verification of an FPGA using automated tools","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W2111427553","doi":"https://doi.org/10.1145/1046192.1046220","mag":"2111427553"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046220","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046220","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091896297","display_name":"Ian Kuon","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ian Kuon","raw_affiliation_strings":["University of Toronto, Toronto, Ontario, Canada","* University of Toronto, Toronto, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, Ontario, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"* University of Toronto, Toronto, Ontario, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081716349","display_name":"Aaron Egier","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Aaron Egier","raw_affiliation_strings":["University of Toronto, Toronto, Ontario, Canada","* University of Toronto, Toronto, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, Ontario, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"* University of Toronto, Toronto, Ontario, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090184149","display_name":"Jonathan Rose","orcid":"https://orcid.org/0000-0002-3551-2175"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jonathan Rose","raw_affiliation_strings":["University of Toronto, Toronto, Ontario, Canada","* University of Toronto, Toronto, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, Ontario, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"* University of Toronto, Toronto, Ontario, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5091896297"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":6.4023,"has_fulltext":false,"cited_by_count":51,"citation_normalized_percentile":{"value":0.96727981,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"215","last_page":"226"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.887633204460144},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7262428998947144},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6429151296615601},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6074541807174683},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5993465781211853},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5599043965339661},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.5403267741203308},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5325497388839722},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5270084142684937},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.45595741271972656},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4480550289154053},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.44207072257995605},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4371795058250427},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4241538941860199},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3855443298816681},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.1998193860054016},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15496578812599182},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15456584095954895},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.09548148512840271}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.887633204460144},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7262428998947144},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6429151296615601},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6074541807174683},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5993465781211853},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5599043965339661},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.5403267741203308},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5325497388839722},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5270084142684937},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.45595741271972656},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4480550289154053},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.44207072257995605},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4371795058250427},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4241538941860199},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3855443298816681},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.1998193860054016},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15496578812599182},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15456584095954895},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.09548148512840271},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1046192.1046220","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046220","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.65.1411","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.65.1411","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~jayar/pubs/kuon/kuonfpga05.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5600000023841858}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310709","display_name":"CMC Microsystems","ror":"https://ror.org/03k70ea39"},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W28973634","https://openalex.org/W124656286","https://openalex.org/W1523051745","https://openalex.org/W1553829507","https://openalex.org/W1576693034","https://openalex.org/W1814902868","https://openalex.org/W1956681806","https://openalex.org/W2024060531","https://openalex.org/W2038318386","https://openalex.org/W2045726766","https://openalex.org/W2050973642","https://openalex.org/W2094806828","https://openalex.org/W2105715355","https://openalex.org/W2109656299","https://openalex.org/W2121903852","https://openalex.org/W2127936519","https://openalex.org/W2138986335","https://openalex.org/W2139637699","https://openalex.org/W2160474882","https://openalex.org/W2162628682","https://openalex.org/W2185217550","https://openalex.org/W2987803397"],"related_works":["https://openalex.org/W4321510758","https://openalex.org/W4224070063","https://openalex.org/W2156243217","https://openalex.org/W2109413979","https://openalex.org/W2098497894","https://openalex.org/W4241744477","https://openalex.org/W2060392256","https://openalex.org/W2223186343","https://openalex.org/W2165817382","https://openalex.org/W2475655475"],"abstract_inverted_index":{"Creating":[0],"a":[1,5,38,43,106,131,143,163,226,237],"new":[2,39,74],"FPGA":[3,40,120,138,171,239],"is":[4,47,52,86,125,175,232,264],"challenging":[6],"undertaking":[7],"because":[8,49],"of":[9,105,110,117,130,155,169,202,262],"the":[10,50,59,69,99,115,118,128,153,170,188,194,243,248],"significant":[11,213,244],"effort":[12],"that":[13,112,134,145,190,210,222,231,255,259],"must":[14],"be":[15,63,147],"spent":[16],"on":[17],"circuit":[18,197],"design,":[19,198],"layout":[20,144,184,199,227,261],"and":[21,57,161,200,247,266],"verification.":[22],"It":[23],"currently":[24],"takes":[25],"approximately":[26],"50":[27],"to":[28,35,71,83,97,126,141,183],"200":[29],"person":[30],"years":[31],"from":[32],"architecture":[33,79,139,182,195],"definition":[34],"tape-out":[36],"for":[37,73,149],"family.":[41],"Such":[42],"lengthy":[44],"development":[45],"time":[46,70,245],"necessary":[48],"process":[51,61,101],"primarily":[53],"done":[54],"manually.":[55],"Simplifying":[56],"shortening":[58],"design":[60,216],"would":[62],"advantageous":[64],"since":[65],"it":[66],"could":[67],"reduce":[68],"market":[72],"FPGAs":[75,263],"while":[76],"also":[77],"enhancing":[78],"explorations.":[80],"One":[81],"way":[82],"accomplish":[84],"this":[85,91,156,178,181,256],"through":[87],"automation":[88],"and,":[89],"in":[90,114,193,215],"paper,":[92],"we":[93,186,220,223,253],"describe":[94],"our":[95],"efforts":[96],"automate":[98],"entire":[100],"by":[102,158],"making":[103],"use":[104],"previously":[107],"developed":[108],"set":[109],"tools":[111,230],"assist":[113],"creation":[116],"repeatable":[119],"tile":[121],"[25].":[122],"Our":[123],"aim":[124],"demonstrate":[127,221],"feasibility":[129,154],"CAD":[132],"flow":[133],"uses":[135],"an":[136,204],"input":[137],"description":[140],"generate":[142],"can":[146,224],"sent":[148],"fabrication.":[150],"We":[151,208],"prove":[152],"proposition":[157],"actually":[159],"designing":[160],"fabricating":[162],"complete":[164],"FPGA.":[165,207],"Initial":[166],"functional":[167],"testing":[168],"appears":[172],"promising":[173],"but":[174],"inconclusive":[176],"at":[177],"time.":[179,217],"Through":[180],"process,":[185],"investigate":[187],"issues":[189],"are":[191,212],"faced":[192],"selection,":[196],"verification":[201],"such":[203],"automatically":[205],"produced":[206],"found":[209],"there":[211],"savings":[214,246],"As":[218],"well,":[219],"produce":[225],"using":[228],"automated":[229,260],"only":[233],"36%":[234],"larger":[235],"than":[236],"commercial":[238],"device":[240],"layout.":[241],"Given":[242],"relatively":[249],"minor":[250],"area":[251],"penalty,":[252],"feel":[254],"work":[257],"demonstrates":[258],"practical":[265],"advantageous.":[267]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}