{"id":"https://openalex.org/W2144915188","doi":"https://doi.org/10.1145/1046192.1046218","title":"Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability","display_name":"Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W2144915188","doi":"https://doi.org/10.1145/1046192.1046218","mag":"2144915188"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046218","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046218","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101026950","display_name":"Yan Lin","orcid":"https://orcid.org/0009-0001-4169-6150"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yan Lin","raw_affiliation_strings":["University of California, Los Angeles, CA","University of California, Los Angeles. CA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"University of California, Los Angeles. CA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100325808","display_name":"Fei Li","orcid":"https://orcid.org/0000-0002-2870-3010"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fei Li","raw_affiliation_strings":["University of California, Los Angeles, CA","University of California, Los Angeles. CA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"University of California, Los Angeles. CA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008695429","display_name":"Lei He","orcid":"https://orcid.org/0000-0002-5266-3805"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lei He","raw_affiliation_strings":["University of California, Los Angeles, CA","University of California, Los Angeles. CA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"University of California, Los Angeles. CA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101026950"],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":8.3434,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.97847414,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"199","last_page":"207"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8338741064071655},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7026352286338806},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6445422172546387},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6315104365348816},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6297087669372559},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6125819683074951},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5325435996055603},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5021767616271973},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4962635636329651},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4586174488067627},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.449080228805542},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.43043699860572815},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4291672110557556},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4134595990180969},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4013976752758026},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3614981770515442},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19244495034217834},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1287238597869873},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08837410807609558}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8338741064071655},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7026352286338806},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6445422172546387},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6315104365348816},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6297087669372559},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6125819683074951},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5325435996055603},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5021767616271973},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4962635636329651},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4586174488067627},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.449080228805542},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.43043699860572815},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4291672110557556},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4134595990180969},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4013976752758026},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3614981770515442},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19244495034217834},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1287238597869873},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08837410807609558},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1046192.1046218","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046218","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.118.8368","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.118.8368","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.ucla.edu/~ylin/publications/fpga05.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1719300925","https://openalex.org/W2013409221","https://openalex.org/W2045726766","https://openalex.org/W2097521167","https://openalex.org/W2101356024","https://openalex.org/W2113645429","https://openalex.org/W2120397377","https://openalex.org/W2124021899","https://openalex.org/W2125469204","https://openalex.org/W2135250302","https://openalex.org/W2137978438","https://openalex.org/W2150549968","https://openalex.org/W2151731855","https://openalex.org/W2159142998","https://openalex.org/W2161521898"],"related_works":["https://openalex.org/W2135636985","https://openalex.org/W3023652529","https://openalex.org/W2480852620","https://openalex.org/W2182398074","https://openalex.org/W2125609625","https://openalex.org/W2071567894","https://openalex.org/W2167086449","https://openalex.org/W2024574431","https://openalex.org/W4239932082","https://openalex.org/W4237841534"],"abstract_inverted_index":{"Vdd-programmable":[0,42,64,78],"FPGAs":[1],"have":[2],"been":[3],"proposed":[4],"recently":[5],"to":[6,56,85,90,135],"reduce":[7],"FPGA":[8,35,65],"power,":[9],"where":[10],"Vdd":[11],"levels":[12],"can":[13,24],"be":[14,25],"customized":[15],"for":[16,139],"different":[17],"circuit":[18,22],"elements":[19,23],"and":[20,38,58,81,109],"unused":[21],"power-gated.":[26],"In":[27],"this":[28],"paper,":[29],"we":[30,62],"first":[31],"develop":[32],"an":[33],"accurate":[34],"power":[36,54],"model":[37,55],"then":[39],"design":[40],"novel":[41],"interconnect":[43],"switches":[44],"with":[45,105],"minimum":[46],"number":[47],"of":[48],"configuration":[49],"SRAM":[50,111],"cells.":[51],"Applying":[52],"our":[53,75],"placed":[57],"routed":[59],"benchmark":[60],"circuits,":[61],"evaluate":[63],"architecture":[66,73,88,97],"using":[67],"the":[68,86,91,95,99,125,136],"new":[69],"switches.":[70],"The":[71],"best":[72,96],"in":[74],"study":[76],"uses":[77],"logic":[79],"blocks":[80],"Vdd-gateable":[82],"interconnects.":[83],"Compared":[84],"baseline":[87],"similar":[89],"leading":[92],"commercial":[93],"architecture,":[94],"reduces":[98],"minimal":[100],"energy-delay":[101],"product":[102],"by":[103],"44.14%":[104],"48%":[106],"area":[107],"overhead":[108],"3%":[110],"cell":[112],"increase.":[113],"Our":[114],"evaluation":[115],"results":[116],"also":[117],"show":[118],"that":[119],"LUT":[120,130],"size":[121,131],"4":[122],"always":[123,133],"gives":[124],"lowest":[126],"energy":[127],"consumption":[128],"while":[129],"7":[132],"leads":[134],"highest":[137],"performance":[138],"all":[140],"evaluated":[141],"architectures.":[142]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
