{"id":"https://openalex.org/W2030641935","doi":"https://doi.org/10.1145/1046192.1046211","title":"Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs","display_name":"Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W2030641935","doi":"https://doi.org/10.1145/1046192.1046211","mag":"2030641935"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046211","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005697949","display_name":"Nicola Campregher","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Nicola Campregher","raw_affiliation_strings":["Imperial College London,UK","Imperial College , London, UK"],"affiliations":[{"raw_affiliation_string":"Imperial College London,UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College , London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Imperial College London,UK","Imperial College , London, UK"],"affiliations":[{"raw_affiliation_string":"Imperial College London,UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College , London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George A. Constantinides","raw_affiliation_strings":["Imperial College London,UK","Imperial College , London, UK"],"affiliations":[{"raw_affiliation_string":"Imperial College London,UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College , London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075098623","display_name":"Milan Vasilko","orcid":null},"institutions":[{"id":"https://openalex.org/I9300472","display_name":"Bournemouth University","ror":"https://ror.org/05wwcw481","country_code":"GB","type":"education","lineage":["https://openalex.org/I9300472"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Milan Vasilko","raw_affiliation_strings":["Bournemouth University, UK"],"affiliations":[{"raw_affiliation_string":"Bournemouth University, UK","institution_ids":["https://openalex.org/I9300472"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5005697949"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":3.8671,"has_fulltext":false,"cited_by_count":58,"citation_normalized_percentile":{"value":0.9332483,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"138","last_page":"148"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.7688448429107666},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7319415807723999},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6067476272583008},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5307878255844116},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.43907877802848816},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4142574667930603},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.384773313999176},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3742259442806244},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3375649154186249},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2290768325328827},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2149418592453003},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1661352813243866},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08501318097114563}],"concepts":[{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.7688448429107666},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7319415807723999},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6067476272583008},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5307878255844116},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.43907877802848816},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4142574667930603},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.384773313999176},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3742259442806244},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3375649154186249},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2290768325328827},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2149418592453003},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1661352813243866},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08501318097114563},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1046192.1046211","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320314786","display_name":"Xilinx","ror":"https://ror.org/01rb7bk56"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1492200690","https://openalex.org/W1558796979","https://openalex.org/W1597088765","https://openalex.org/W1639141794","https://openalex.org/W1905355278","https://openalex.org/W1990929003","https://openalex.org/W2021792911","https://openalex.org/W2034034477","https://openalex.org/W2037926253","https://openalex.org/W2041090186","https://openalex.org/W2069898567","https://openalex.org/W2089238344","https://openalex.org/W2096535541","https://openalex.org/W2099992500","https://openalex.org/W2101472024","https://openalex.org/W2103825209","https://openalex.org/W2104136310","https://openalex.org/W2110864115","https://openalex.org/W2120295190","https://openalex.org/W2133857907","https://openalex.org/W2135225513","https://openalex.org/W2149930993","https://openalex.org/W2263452264","https://openalex.org/W2321486756","https://openalex.org/W2628405439","https://openalex.org/W2884479736"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W4249035840","https://openalex.org/W2766970861","https://openalex.org/W2008827750"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"analysis":[4],"of":[5],"the":[6,27,35,41,49,61,67,72],"potential":[7,84],"yield":[8,21,52,69,87],"loss":[9,53],"in":[10,16,31,51,57,60],"FPGA":[11,28],"due":[12,54],"to":[13,25,33,47,55],"random":[14],"defects":[15,56],"metal":[17],"layers.":[18],"A":[19],"proven":[20],"model":[22],"is":[23,64,78,99],"adapted":[24],"target":[26],"interconnect":[29,58],"layers":[30,59],"order":[32],"predict":[34],"manufacturing":[36],"yield.":[37],"Defect":[38],"parameters":[39],"from":[40],"2003":[42],"SIA":[43],"roadmap":[44],"are":[45],"used":[46],"investigate":[48],"trend":[50],"future.":[62],"It":[63],"shown":[65],"that":[66],"low":[68],"predicted":[70],"for":[71,81],"45nm":[73],"technology":[74],"node":[75],"and":[76,95],"beyond":[77],"a":[79],"cause":[80],"concern.":[82],"The":[83],"impact":[85],"on":[86],"using":[88],"two":[89],"different":[90],"approaches,":[91],"namely":[92],"redundant":[93],"circuits":[94],"fault":[96],"tolerant":[97],"design,":[98],"also":[100],"presented.":[101]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}