{"id":"https://openalex.org/W2049960281","doi":"https://doi.org/10.1145/1046192.1046198","title":"Skew-programmable clock design for FPGA and skew-aware placement","display_name":"Skew-programmable clock design for FPGA and skew-aware placement","publication_year":2005,"publication_date":"2005-02-20","ids":{"openalex":"https://openalex.org/W2049960281","doi":"https://doi.org/10.1145/1046192.1046198","mag":"2049960281"},"language":"en","primary_location":{"id":"doi:10.1145/1046192.1046198","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046198","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112744422","display_name":"Chao-Yang Yeh","orcid":null},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chao-Yang Yeh","raw_affiliation_strings":["University of California, Santa Barbara, CA","University of California, Santa Barbara, Ca#TAB#"],"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, CA","institution_ids":["https://openalex.org/I154570441"]},{"raw_affiliation_string":"University of California, Santa Barbara, Ca#TAB#","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063371595","display_name":"Malgorzata Marek-Sadowska","orcid":"https://orcid.org/0000-0002-3934-7031"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Malgorzata Marek-Sadowska","raw_affiliation_strings":["University of California, Santa Barbara, CA","University of California, Santa Barbara, Ca#TAB#"],"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, CA","institution_ids":["https://openalex.org/I154570441"]},{"raw_affiliation_string":"University of California, Santa Barbara, Ca#TAB#","institution_ids":["https://openalex.org/I154570441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5112744422"],"corresponding_institution_ids":["https://openalex.org/I154570441"],"apc_list":null,"apc_paid":null,"fwci":0.7114,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.73300643,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"33","last_page":"40"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7944937944412231},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7468175888061523},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6987148523330688},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6941299438476562},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6299924850463867},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6053491234779358},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5849557518959045},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5137680768966675},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5135867595672607},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.49377116560935974},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32606416940689087},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.0810638964176178}],"concepts":[{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7944937944412231},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7468175888061523},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6987148523330688},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6941299438476562},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6299924850463867},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6053491234779358},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5849557518959045},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5137680768966675},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5135867595672607},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.49377116560935974},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32606416940689087},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0810638964176178},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1046192.1046198","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1046192.1046198","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1496592812","https://openalex.org/W1987786682","https://openalex.org/W2010997912","https://openalex.org/W2011778848","https://openalex.org/W2048796234","https://openalex.org/W2094806828","https://openalex.org/W2105565203","https://openalex.org/W2118482092","https://openalex.org/W2135347849","https://openalex.org/W2139071021","https://openalex.org/W2170510975","https://openalex.org/W2173972090","https://openalex.org/W4255469943","https://openalex.org/W6647386927"],"related_works":["https://openalex.org/W2003180247","https://openalex.org/W2116514610","https://openalex.org/W2144282137","https://openalex.org/W2032549010","https://openalex.org/W2391115906","https://openalex.org/W2292909929","https://openalex.org/W1514283284","https://openalex.org/W2127379989","https://openalex.org/W2117814846","https://openalex.org/W2112814021"],"abstract_inverted_index":{"In":[0,85,177],"this":[1,86],"paper,":[2],"we":[3,20,88,115,156],"propose":[4,89],"a":[5,75,110,159],"skew-programmable":[6],"clock-routing":[7],"architecture.":[8],"The":[9],"skews":[10],"can":[11,53,105,138,157],"be":[12,106,139],"adjusted":[13],"using":[14,122,152],"programmable":[15],"delay":[16],"elements":[17],"(PDEs)":[18],"which":[19,44,94],"insert":[21],"into":[22],"the":[23,99,117,124,130,153,180],"clock":[24],"trees.":[25],"We":[26],"develop":[27],"efficient,":[28],"shortest-path-based":[29],"algorithms":[30,93],"for":[31,40,163],"programming":[32],"PDEs":[33],"to":[34,70,97,141],"optimize":[35],"timing.":[36],"Unlike":[37],"previous":[38],"methods":[39],"FPGA":[41],"skew":[42,126,145,165],"optimization":[43,127,146,166],"require":[45],"large":[46,55],"power":[47,191],"and":[48,83,129,137,167,193],"routing":[49],"penalty,":[50],"our":[51,120,173],"method":[52,128],"achieve":[54],"timing":[56,63,100,161],"improvement":[57,162,171],"with":[58],"small":[59],"overhead.":[60,199],"Typically,":[61],"if":[62],"requirements":[64],"are":[65,134],"tight,":[66],"placers":[67],"make":[68],"efforts":[69],"satisfy":[71],"them,":[72],"often":[73],"at":[74],"cost":[76,181],"of":[77,119,182,197],"compromising":[78],"routability,":[79],"total":[80],"wire":[81],"length,":[82],"power.":[84],"work,":[87],"novel":[90],"clock-skew-aware":[91],"placement":[92,132,175],"allow":[95],"us":[96],"relax":[98],"constraints":[101],"during":[102],"placement.":[103],"Timing":[104],"later":[107],"optimized":[108],"as":[109,187],"post":[111],"process.":[112],"Even":[113],"though":[114],"demonstrate":[116],"efficiency":[118],"approach":[121],"FPGAs,":[123],"new":[125,131,154],"algorithm":[133],"quite":[135],"general":[136],"applied":[140],"any":[142],"general,":[143],"topology-constrained":[144],"problem.":[147],"Experimental":[148],"results":[149],"indicate":[150],"that":[151],"clock-architecture":[155],"obtain":[158],"22%":[160],"post-layout":[164],"an":[168],"additional":[169],"21%":[170],"from":[172],"skew-aware":[174],"algorithm.":[176],"one":[178],"fabric,":[179],"added":[183],"logic":[184],"is":[185],"2.19%":[186],"measured":[188],"by":[189],"dynamic":[190],"dissipation,":[192],"0.85%":[194],"in":[195],"terms":[196],"area":[198]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}