{"id":"https://openalex.org/W2009886514","doi":"https://doi.org/10.1145/1016568.1016625","title":"A switch architecture and signal synchronization for GALS system-on-chips","display_name":"A switch architecture and signal synchronization for GALS system-on-chips","publication_year":2004,"publication_date":"2004-09-04","ids":{"openalex":"https://openalex.org/W2009886514","doi":"https://doi.org/10.1145/1016568.1016625","mag":"2009886514"},"language":"en","primary_location":{"id":"doi:10.1145/1016568.1016625","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016625","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002067478","display_name":"Peter Zipf","orcid":"https://orcid.org/0000-0003-4725-4246"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Peter Zipf","raw_affiliation_strings":["Darmstadt University of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Darmstadt University of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055033918","display_name":"Heiko Hinkelmann","orcid":"https://orcid.org/0000-0003-0982-034X"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Heiko Hinkelmann","raw_affiliation_strings":["Darmstadt University of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Darmstadt University of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048712663","display_name":"Adeel Ashraf","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Adeel Ashraf","raw_affiliation_strings":["Darmstadt University of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Darmstadt University of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002162776","display_name":"Manfred Glesner","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Manfred Glesner","raw_affiliation_strings":["Darmstadt University of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Darmstadt University of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":1.2477,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.83777778,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"210","last_page":"215"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8736885786056519},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7112337350845337},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7015045881271362},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6804889440536499},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5784081816673279},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.5755243897438049},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5210130214691162},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5164032578468323},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.49702218174934387},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.4764026701450348},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4722948372364044},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.41828984022140503},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4158300757408142},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3882986009120941},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.36931532621383667},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3406893014907837},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.24728578329086304},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.18711340427398682},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16787254810333252},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.16679900884628296},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1340913474559784}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8736885786056519},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7112337350845337},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7015045881271362},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6804889440536499},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5784081816673279},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.5755243897438049},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5210130214691162},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5164032578468323},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.49702218174934387},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.4764026701450348},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4722948372364044},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.41828984022140503},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4158300757408142},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3882986009120941},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.36931532621383667},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3406893014907837},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.24728578329086304},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.18711340427398682},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16787254810333252},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.16679900884628296},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1340913474559784},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1016568.1016625","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016625","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W239283595","https://openalex.org/W1485545475","https://openalex.org/W1520460310","https://openalex.org/W1550917065","https://openalex.org/W1553739034","https://openalex.org/W1666015432","https://openalex.org/W1965748010","https://openalex.org/W1967575124","https://openalex.org/W2068505107","https://openalex.org/W2096749015","https://openalex.org/W2140137324","https://openalex.org/W2141242940","https://openalex.org/W2160642395","https://openalex.org/W6631072185"],"related_works":["https://openalex.org/W4312516786","https://openalex.org/W60393894","https://openalex.org/W2384756109","https://openalex.org/W364924225","https://openalex.org/W158833317","https://openalex.org/W2237508561","https://openalex.org/W2325117947","https://openalex.org/W628161287","https://openalex.org/W1993985975","https://openalex.org/W794031490"],"abstract_inverted_index":{"Increasing":[0],"power":[1],"consumption":[2],"and":[3,97],"growing":[4],"design":[5,13],"effort":[6],"are":[7,120],"considered":[8],"limiting":[9],"factors":[10],"in":[11,72,110],"the":[12,46,85,88,98,101],"of":[14,45,87,100,115],"chip-wide":[15],"synchronous":[16],"System-on-Chip":[17],"designs.":[18],"The":[19,91],"attempt":[20],"to":[21,27,105],"get":[22],"over":[23],"these":[24],"problems":[25],"leads":[26],"an":[28],"intensified":[29],"look":[30],"at":[31,84],"asynchronous":[32,42,66],"communication":[33],"solutions,":[34],"sometimes":[35],"based":[36],"on":[37],"Network-on-Chips.":[38],"Despite":[39],"this":[40],"basically":[41],"approach,":[43],"most":[44],"actual":[47],"research":[48],"work":[49],"is":[50,95,108],"not":[51],"supporting":[52],"a":[53,59,63,76,81,116],"globally":[54,65],"genuinely-asynchronous":[55],"solution.":[56],"We":[57],"present":[58],"modular":[60],"switch":[61,74,93],"for":[62],"true":[64],"interconnect":[67,89],"network.":[68,90],"Independent":[69],"clock":[70,78,83],"generators":[71],"each":[73],"maintain":[75],"local":[77],"thus":[79],"avoiding":[80],"global":[82],"level":[86],"general":[92],"architecture":[94],"described":[96],"integration":[99],"synchronization":[102],"technique":[103],"used":[104],"resolve":[106],"metastability":[107],"discussed":[109],"detail.":[111],"First":[112],"synthesis":[113],"results":[114],"prototypical":[117],"VLSI":[118],"implementation":[119],"presented.":[121]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
