{"id":"https://openalex.org/W2124522903","doi":"https://doi.org/10.1145/1016568.1016620","title":"A programmable cellular neural network circuit","display_name":"A programmable cellular neural network circuit","publication_year":2004,"publication_date":"2004-09-04","ids":{"openalex":"https://openalex.org/W2124522903","doi":"https://doi.org/10.1145/1016568.1016620","mag":"2124522903"},"language":"en","primary_location":{"id":"doi:10.1145/1016568.1016620","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016620","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070772693","display_name":"Michel Leong","orcid":null},"institutions":[{"id":"https://openalex.org/I4387152517","display_name":"Instituto Superior T\u00e9cnico","ror":"https://ror.org/03db2by73","country_code":null,"type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4387152517"]},{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"Michel Leong","raw_affiliation_strings":["Instituto Superior T\u00e9cnico / INESC-ID Lisboa, Lisboa, Portugal"],"affiliations":[{"raw_affiliation_string":"Instituto Superior T\u00e9cnico / INESC-ID Lisboa, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I4387152517"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012679115","display_name":"Pedro Fernando da Costa Vasconcelos","orcid":"https://orcid.org/0000-0002-6603-5527"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I4387152517","display_name":"Instituto Superior T\u00e9cnico","ror":"https://ror.org/03db2by73","country_code":null,"type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4387152517"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Pedro Vasconcelos","raw_affiliation_strings":["Instituto Superior T\u00e9cnico / INESC-ID Lisboa, Lisboa, Portugal"],"affiliations":[{"raw_affiliation_string":"Instituto Superior T\u00e9cnico / INESC-ID Lisboa, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I4387152517"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047549981","display_name":"Jorge Fernandes","orcid":"https://orcid.org/0000-0002-4916-5637"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I4387152517","display_name":"Instituto Superior T\u00e9cnico","ror":"https://ror.org/03db2by73","country_code":null,"type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4387152517"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Jorge R. Fernandes","raw_affiliation_strings":["Instituto Superior T\u00e9cnico / INESC-ID Lisboa, Lisboa, Portugal"],"affiliations":[{"raw_affiliation_string":"Instituto Superior T\u00e9cnico / INESC-ID Lisboa, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I4387152517"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077537777","display_name":"Leonel Sousa","orcid":"https://orcid.org/0000-0002-8066-221X"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I4387152517","display_name":"Instituto Superior T\u00e9cnico","ror":"https://ror.org/03db2by73","country_code":null,"type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4387152517"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Leonel Sousa","raw_affiliation_strings":["Instituto Superior T\u00e9cnico / INESC-ID Lisboa, Lisboa, Portugal"],"affiliations":[{"raw_affiliation_string":"Instituto Superior T\u00e9cnico / INESC-ID Lisboa, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I4387152517"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5070772693"],"corresponding_institution_ids":["https://openalex.org/I121345201","https://openalex.org/I4387152517"],"apc_list":null,"apc_paid":null,"fwci":0.4635,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.72085637,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"186","last_page":"191"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11347","display_name":"Neural Networks Stability and Synchronization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11347","display_name":"Neural Networks Stability and Synchronization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7389767169952393},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6272292733192444},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5896660685539246},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.5747686624526978},{"id":"https://openalex.org/keywords/cellular-neural-network","display_name":"Cellular neural network","score":0.5715870261192322},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5363693237304688},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5122713446617126},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5039343237876892},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.4852199852466583},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.4791219234466553},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.46932169795036316},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4688701927661896},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.4459536373615265},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.43630748987197876},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4182285964488983},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41035839915275574},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4053979516029358},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40186041593551636},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.30535435676574707},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.21267178654670715},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1837320327758789},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1780954897403717}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7389767169952393},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6272292733192444},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5896660685539246},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.5747686624526978},{"id":"https://openalex.org/C812465","wikidata":"https://www.wikidata.org/wiki/Q5058375","display_name":"Cellular neural network","level":3,"score":0.5715870261192322},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5363693237304688},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5122713446617126},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5039343237876892},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.4852199852466583},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.4791219234466553},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.46932169795036316},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4688701927661896},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.4459536373615265},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.43630748987197876},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4182285964488983},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41035839915275574},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4053979516029358},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40186041593551636},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.30535435676574707},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.21267178654670715},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1837320327758789},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1780954897403717},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1016568.1016620","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016620","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W13762197","https://openalex.org/W1502859127","https://openalex.org/W2056717940","https://openalex.org/W2099679337","https://openalex.org/W2101185616","https://openalex.org/W2130407967","https://openalex.org/W2133773098","https://openalex.org/W2160121923","https://openalex.org/W2306062873","https://openalex.org/W3203011645","https://openalex.org/W6664873640","https://openalex.org/W6683695198"],"related_works":["https://openalex.org/W4242258007","https://openalex.org/W2155285526","https://openalex.org/W2007222089","https://openalex.org/W2394022884","https://openalex.org/W2185815555","https://openalex.org/W2071235072","https://openalex.org/W1924227955","https://openalex.org/W4242038055","https://openalex.org/W1493881961","https://openalex.org/W2128579103"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"propose":[4],"and":[5,31,36,45,54],"develop":[6],"a":[7,19,57,64],"fully":[8],"programmable":[9,17],"CNN":[10,13,67],"circuit.":[11],"The":[12,61,75],"coefficients":[14],"are":[15,34,52,77],"digitally":[16],"using":[18,70],"Digital":[20],"to":[21],"Analog":[22],"Converter":[23],"(DAC),":[24],"resulting":[25],"in":[26],"added":[27],"flexibility.CNNs":[28],"with":[29,43,56,79],"4x4":[30,66],"16x16":[32],"cells":[33],"designed":[35,53,69],"tested,":[37],"exhibiting":[38],"good":[39],"accuracy":[40],"when":[41],"compared":[42],"Matlab":[44],"Java":[46],"applications":[47],"for":[48],"computing":[49],"CNNs.All":[50],"circuits":[51,76],"implemented":[55],"0.35um":[58],"CMOS":[59],"technology.":[60],"layout":[62],"of":[63],"full":[65],"was":[68],"Cadence":[71],"Design":[72],"Framework":[73],"II.":[74],"simulated":[78],"Pspice/Spectre.":[80]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
