{"id":"https://openalex.org/W1976802210","doi":"https://doi.org/10.1145/1016568.1016591","title":"TheoSim","display_name":"TheoSim","publication_year":2004,"publication_date":"2004-09-04","ids":{"openalex":"https://openalex.org/W1976802210","doi":"https://doi.org/10.1145/1016568.1016591","mag":"1976802210"},"language":"en","primary_location":{"id":"doi:10.1145/1016568.1016591","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016591","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010015399","display_name":"Ghiath Al Sammane","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"G. Al Sammane","raw_affiliation_strings":["TIMA Laboratory, VDS Group, Grenoble Cedex, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, VDS Group, Grenoble Cedex, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088595514","display_name":"Julien Schmaltz","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J. Schmaltz","raw_affiliation_strings":["TIMA Laboratory, VDS Group, Grenoble Cedex, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, VDS Group, Grenoble Cedex, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053069477","display_name":"Diana Toma","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"D. Toma","raw_affiliation_strings":["TIMA Laboratory, VDS Group, Grenoble Cedex, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, VDS Group, Grenoble Cedex, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051595680","display_name":"P. Ostier","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"P. Ostier","raw_affiliation_strings":["TIMA Laboratory, VDS Group, Grenoble Cedex, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, VDS Group, Grenoble Cedex, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063371658","display_name":"D. Borrione","orcid":"https://orcid.org/0000-0002-4856-453X"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"D. Borrione","raw_affiliation_strings":["TIMA Laboratory, VDS Group, Grenoble Cedex, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, VDS Group, Grenoble Cedex, France","institution_ids":["https://openalex.org/I4210087012"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210087012"],"apc_list":null,"apc_paid":null,"fwci":0.2651,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.55270864,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"60","last_page":"65"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7266116738319397},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4422565698623657},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.42014461755752563},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4116089940071106},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3884274959564209},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3556555509567261}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7266116738319397},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4422565698623657},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.42014461755752563},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4116089940071106},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3884274959564209},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3556555509567261}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1016568.1016591","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016591","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7400000095367432,"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W386590889","https://openalex.org/W1484599239","https://openalex.org/W1488659932","https://openalex.org/W1547263332","https://openalex.org/W1557209036","https://openalex.org/W1590405504","https://openalex.org/W1600735021","https://openalex.org/W1601167865","https://openalex.org/W1797377815","https://openalex.org/W2045261241","https://openalex.org/W2063169916","https://openalex.org/W2069300761","https://openalex.org/W2111927499","https://openalex.org/W2132727849","https://openalex.org/W2158114636","https://openalex.org/W2170511114","https://openalex.org/W2255815563","https://openalex.org/W3010782316","https://openalex.org/W4251912342","https://openalex.org/W6613206214","https://openalex.org/W6630281740","https://openalex.org/W6683379945"],"related_works":["https://openalex.org/W4231937131","https://openalex.org/W323219885","https://openalex.org/W2063928587","https://openalex.org/W1487966966","https://openalex.org/W1589342014","https://openalex.org/W1480341462","https://openalex.org/W598950423","https://openalex.org/W4256673449","https://openalex.org/W4292559016","https://openalex.org/W61995002"],"abstract_inverted_index":{"TheoSim":[0],"is":[1],"a":[2,60],"symbolic":[3],"verifiation":[4],"tool":[5],"that":[6],"fills":[7],"the":[8,11,17,23,29,32,52,55],"gap":[9],"between":[10],"simulation":[12],"of":[13,19,25,31,37,43,54,59],"test":[14],"cases,":[15],"and":[16,28],"use":[18],"theorem":[20],"provers,":[21],"for":[22],"validation":[24],"initial":[26],"specifications,":[27],"exploration":[30],"very":[33],"first":[34,56],"design":[35,57],"steps":[36],"digital":[38],"integrated":[39],"systems.":[40],"The":[41],"principles":[42],"Theosim":[44],"are":[45],"presented,":[46],"followed":[47],"by":[48],"its":[49],"application":[50],"to":[51],"verification":[53],"step":[58],"state-of-the-art":[61],"network":[62],"on":[63],"chip":[64],"architecture.":[65]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2016-06-24T00:00:00"}
