{"id":"https://openalex.org/W1967938402","doi":"https://doi.org/10.1145/1016568.1016572","title":"Advances and trends in FPGA design","display_name":"Advances and trends in FPGA design","publication_year":2004,"publication_date":"2004-09-04","ids":{"openalex":"https://openalex.org/W1967938402","doi":"https://doi.org/10.1145/1016568.1016572","mag":"1967938402"},"language":"en","primary_location":{"id":"doi:10.1145/1016568.1016572","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016572","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038450823","display_name":"Mike Hutton","orcid":"https://orcid.org/0009-0009-0139-7242"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mike Hutton","raw_affiliation_strings":["Altera, San Jose, CA","[Altera Corp., San Jose, CA, USA]"],"affiliations":[{"raw_affiliation_string":"Altera, San Jose, CA","institution_ids":["https://openalex.org/I22433950"]},{"raw_affiliation_string":"[Altera Corp., San Jose, CA, USA]","institution_ids":["https://openalex.org/I22433950"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5038450823"],"corresponding_institution_ids":["https://openalex.org/I22433950"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10178781,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"8","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9857000112533569,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9708999991416931,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9342229962348938},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7151367664337158},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6796998381614685},{"id":"https://openalex.org/keywords/mainstream","display_name":"Mainstream","score":0.6700554490089417},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5722206830978394},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5376907587051392},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5323116183280945},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5051732659339905},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4223017394542694},{"id":"https://openalex.org/keywords/political-science","display_name":"Political science","score":0.055182188749313354}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9342229962348938},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7151367664337158},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6796998381614685},{"id":"https://openalex.org/C2777617010","wikidata":"https://www.wikidata.org/wiki/Q18957","display_name":"Mainstream","level":2,"score":0.6700554490089417},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5722206830978394},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5376907587051392},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5323116183280945},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5051732659339905},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4223017394542694},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.055182188749313354},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1016568.1016572","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016572","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W2113648965","https://openalex.org/W2984236338","https://openalex.org/W2155484023","https://openalex.org/W4200391368","https://openalex.org/W2388221044","https://openalex.org/W2619213283","https://openalex.org/W3117064361","https://openalex.org/W2057745131"],"abstract_inverted_index":{"This":[0],"talk":[1],"will":[2,19],"give":[3],"an":[4],"overview":[5],"of":[6,12,37],"emerging":[7],"trends":[8,55],"in":[9,30,56],"the":[10,28,35,45],"architecture":[11],"FPGAs.":[13],"The":[14],"topics":[15],"to":[16],"be":[17],"covered":[18],"include":[20],"new":[21],"FPGA":[22,38],"architectures":[23,39],"and":[24,42,49,52,54],"upcoming":[25],"research":[26],"topics,":[27],"growth":[29],"FPGAs":[31,48],"with":[32],"embedded":[33],"tranceivers,":[34],"segmentation":[36],"into":[40],"mainstream":[41],"low-cost":[43],"families,":[44],"relationships":[46],"between":[47],"structured":[50],"ASICs,":[51],"applications":[53],"CPLDs.":[57]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}