{"id":"https://openalex.org/W2138056366","doi":"https://doi.org/10.1145/1016568.1016571","title":"Leakage power optimization in standard-cell designs","display_name":"Leakage power optimization in standard-cell designs","publication_year":2004,"publication_date":"2004-09-04","ids":{"openalex":"https://openalex.org/W2138056366","doi":"https://doi.org/10.1145/1016568.1016571","mag":"2138056366"},"language":"en","primary_location":{"id":"doi:10.1145/1016568.1016571","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016571","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005432629","display_name":"Enrico Macii","orcid":"https://orcid.org/0000-0001-9046-5618"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Enrico Macii","raw_affiliation_strings":["Politecnico di Torino, Torino, Italy","[Dipt. di Autom. e Inf., Politecnico di Torino, Italy]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"[Dipt. di Autom. e Inf., Politecnico di Torino, Italy]","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5005432629"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17502598,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"7","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.7412388920783997},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7328693270683289},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.7239590883255005},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.7037578821182251},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5724160671234131},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5511986613273621},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5024363994598389},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.47367531061172485},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.46561408042907715},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4640200734138489},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.44694751501083374},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4404095709323883},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.43397021293640137},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43023011088371277},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.40979617834091187},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.36440885066986084},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.354503333568573},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23471277952194214},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.18553176522254944}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.7412388920783997},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7328693270683289},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.7239590883255005},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.7037578821182251},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5724160671234131},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5511986613273621},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5024363994598389},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.47367531061172485},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.46561408042907715},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4640200734138489},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.44694751501083374},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4404095709323883},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.43397021293640137},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43023011088371277},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.40979617834091187},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.36440885066986084},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.354503333568573},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23471277952194214},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.18553176522254944},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1016568.1016571","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016571","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"},{"id":"pmh:oai:porto.polito.it:1500042","is_oa":false,"landing_page_url":"http://porto.polito.it/1500042/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5799999833106995,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2993028905","https://openalex.org/W4242912623","https://openalex.org/W2142651762","https://openalex.org/W2376726667","https://openalex.org/W2543084892","https://openalex.org/W4386859294","https://openalex.org/W2967850598","https://openalex.org/W2357425846","https://openalex.org/W162881505","https://openalex.org/W2304374807"],"abstract_inverted_index":{"Leakage":[0],"power":[1,202],"consumption":[2],"is":[3,27,84,88],"a":[4,65,107,176,183,198],"growing":[5],"concern":[6],"in":[7,133,155],"integrated":[8],"circuit":[9],"design.":[10],"Nanometer":[11],"CMOS":[12],"transistors":[13],"are":[14,39,104,121],"characterized":[15],"by":[16],"significant":[17],"sub-threshold":[18,36,69],"and":[19,23,86,96,135,144],"gate":[20,45],"leakage":[21,37,70,201],"currents":[22,38,46],"feature":[24],"size":[25],"scaling":[26],"exacerbating":[28],"this":[29,60],"problem.":[30],"In":[31],"today's":[32],"technologies":[33],"(i.e.,":[34],"90nm),":[35],"still":[40],"dominant":[41],"with":[42,91],"respect":[43],"to":[44,150,161,206],"(although":[47],"the":[48,52,75,97,124,156,162,167,192,210],"trend":[49],"shows":[50],"that":[51,111],"latter":[53],"grows":[54],"more":[55],"rapidly":[56],"as":[57,147],"technology":[58],"scales).In":[59],"talk,":[61],"we":[62,194],"will":[63,158],"introduce":[64],"complete":[66],"methodology":[67,138,171],"for":[68,115,181],"current":[71],"reduction":[72,199],"based":[73],"on":[74,175,209],"concept":[76],"of":[77,109,126,142,166,178,200],"sleep":[78,163,168],"transistor":[79,102,169],"insertion.":[80],"Our":[81],"insertion":[82,170],"approach":[83],"layout-aware":[85],"it":[87,148],"fully":[89],"compatible":[90],"industry-standard":[92],"row-based":[93],"layout":[94,117],"styles":[95],"supporting":[98],"design":[99,179],"tools.":[100],"Sleep":[101],"cells":[103,110,120],"chosen":[105],"from":[106,204],"library":[108],"has":[112,172],"been":[113,173],"designed":[114],"high":[116],"efficiency.":[118],"These":[119],"inserted":[122],"at":[123],"boundaries":[125],"existing":[127],"cell":[128],"rows,":[129],"causing":[130],"minimal":[131],"disruption":[132],"placement":[134],"routing.":[136],"The":[137],"ensures":[139],"tight":[140],"control":[141],"area":[143],"delay":[145],"overheads,":[146],"allows":[149],"selectively":[151],"choose":[152],"which":[153,182],"gates":[154],"netlist":[157],"be":[159],"connetcted":[160],"transistors.The":[164],"effectiveness":[165],"benchmarked":[174],"set":[177],"examples":[180],"physical":[184],"implementation":[185],"was":[186],"obtained":[187],"through":[188],"commercial":[189],"EDA":[190],"tools;":[191],"results":[193],"have":[195],"achieved":[196],"show":[197],"ranging":[203],"74%":[205],"83%,":[207],"depending":[208],"circuit.":[211]},"counts_by_year":[],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}
