{"id":"https://openalex.org/W2113735758","doi":"https://doi.org/10.1145/1013235.1013259","title":"Delay optimal low-power circuit clustering for FPGAs with dual supply voltages","display_name":"Delay optimal low-power circuit clustering for FPGAs with dual supply voltages","publication_year":2004,"publication_date":"2004-08-09","ids":{"openalex":"https://openalex.org/W2113735758","doi":"https://doi.org/10.1145/1013235.1013259","mag":"2113735758"},"language":"en","primary_location":{"id":"doi:10.1145/1013235.1013259","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1013235.1013259","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 international symposium on Low power electronics and design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056321228","display_name":"Deming Chen","orcid":"https://orcid.org/0000-0002-3016-0270"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Deming Chen","raw_affiliation_strings":["University of California, Los Angeles, CA","Dept. of comput. Sci., California Univ., Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"Dept. of comput. Sci., California Univ., Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102170602","display_name":"Jason Cong","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Cong","raw_affiliation_strings":["University of California, Los Angeles, CA","Dept. of comput. Sci., California Univ., Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"Dept. of comput. Sci., California Univ., Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5056321228"],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":2.3715,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.88624996,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"70","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8454262018203735},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.820173978805542},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6378195881843567},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5655980110168457},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.565199613571167},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5315399169921875},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.49755266308784485},{"id":"https://openalex.org/keywords/low-voltage","display_name":"Low voltage","score":0.44665026664733887},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37137371301651},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.324895441532135},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20514190196990967},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1776236891746521},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16575539112091064},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10849204659461975},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.0907118022441864}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8454262018203735},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.820173978805542},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6378195881843567},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5655980110168457},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.565199613571167},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5315399169921875},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.49755266308784485},{"id":"https://openalex.org/C128624480","wikidata":"https://www.wikidata.org/wiki/Q1504817","display_name":"Low voltage","level":3,"score":0.44665026664733887},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37137371301651},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.324895441532135},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20514190196990967},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1776236891746521},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16575539112091064},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10849204659461975},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0907118022441864},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1145/1013235.1013259","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1013235.1013259","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 international symposium on Low power electronics and design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.112.1935","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.112.1935","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cadlab.cs.ucla.edu/~xfpga/project/p193-chen.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.63.5524","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.63.5524","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cadlab.cs.ucla.edu/~cong/papers/p193-chen.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.67.2131","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.67.2131","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cadlab.cs.ucla.edu/~cong/papers/islped04.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8399999737739563,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1480203124","https://openalex.org/W1982882434","https://openalex.org/W1988118342","https://openalex.org/W2002641171","https://openalex.org/W2004015744","https://openalex.org/W2013409221","https://openalex.org/W2029541370","https://openalex.org/W2039731046","https://openalex.org/W2083201446","https://openalex.org/W2097521167","https://openalex.org/W2101356024","https://openalex.org/W2111756578","https://openalex.org/W2121190917","https://openalex.org/W2132225593","https://openalex.org/W2149513075","https://openalex.org/W2150281391","https://openalex.org/W2151731855","https://openalex.org/W2157661053","https://openalex.org/W2161521898","https://openalex.org/W2163550599"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W2082487009","https://openalex.org/W2373535795","https://openalex.org/W3103262449","https://openalex.org/W3130402546"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,27,33,80,124],"delay":[4,49,56],"optimal":[5],"FPGA":[6,21,122,139],"clustering":[7,42,105,118,137],"algorithm":[8,106],"targeting":[9],"low":[10,34],"power.":[11,77],"We":[12,38,78],"assume":[13],"that":[14,47,103],"the":[15,20,41,45,48,51,54,62,67,87,96,117,132],"configurable":[16],"logic":[17,64],"blocks":[18,65],"of":[19,50,82],"can":[22,70,107],"be":[23,71],"programmed":[24],"using":[25],"either":[26],"high":[28],"supply":[29,35],"voltage":[30,36],"(high-Vdd)":[31],"or":[32],"(low-Vdd).":[37],"carry":[39],"out":[40],"procedure":[43],"with":[44,123],"guarantee":[46],"circuit":[52],"under":[53],"general":[55],"model":[57],"is":[58,131],"optimal,":[59],"and":[60,92],"in":[61],"meantime,":[63],"on":[66,113,135],"non-critical":[68],"paths":[69],"driven":[72],"by":[73,111],"low-Vdd":[74,91],"to":[75,85,94,116],"save":[76],"explore":[79],"set":[81],"dual-Vdd":[83,136],"combinations":[84],"find":[86],"best":[88],"ratio":[89],"between":[90],"high-Vdd":[93],"achieve":[95,108],"largest":[97],"power":[98,109],"reduction.":[99],"Experimental":[100],"results":[101],"show":[102],"our":[104,128],"savings":[110],"20.3%":[112],"average":[114],"compared":[115],"result":[119],"for":[120,138],"an":[121],"single":[125],"high-Vdd.":[126],"To":[127],"knowledge,":[129],"this":[130],"first":[133],"work":[134],"architectures.":[140]},"counts_by_year":[{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}