{"id":"https://openalex.org/W1994364444","doi":"https://doi.org/10.1142/s0129054110007209","title":"ANALOG/MIXED-SIGNAL CIRCUIT VERIFICATION USING MODELS GENERATED FROM SIMULATION TRACES","display_name":"ANALOG/MIXED-SIGNAL CIRCUIT VERIFICATION USING MODELS GENERATED FROM SIMULATION TRACES","publication_year":2010,"publication_date":"2010-03-31","ids":{"openalex":"https://openalex.org/W1994364444","doi":"https://doi.org/10.1142/s0129054110007209","mag":"1994364444"},"language":"en","primary_location":{"id":"doi:10.1142/s0129054110007209","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0129054110007209","pdf_url":null,"source":{"id":"https://openalex.org/S68047077","display_name":"International Journal of Foundations of Computer Science","issn_l":"0129-0541","issn":["0129-0541","1793-6373"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Foundations of Computer Science","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024750161","display_name":"Scott Little","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"SCOTT LITTLE","raw_affiliation_strings":["Freescale Semiconductor, Austin, TX 78729, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Austin, TX 78729, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082821824","display_name":"David Walter","orcid":"https://orcid.org/0000-0001-8781-7176"},"institutions":[{"id":"https://openalex.org/I11786554","display_name":"Virginia State University","ror":"https://ror.org/04esvpn06","country_code":"US","type":"education","lineage":["https://openalex.org/I11786554"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"DAVID WALTER","raw_affiliation_strings":["Virginia State University, Petersburg, VA 23806, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Virginia State University, Petersburg, VA 23806, USA","institution_ids":["https://openalex.org/I11786554"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044836118","display_name":"Kevin L. Jones","orcid":"https://orcid.org/0000-0001-5176-5474"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"KEVIN JONES","raw_affiliation_strings":["University of Utah, Salt Lake City, UT 84112, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, UT 84112, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111386695","display_name":"Chris J. Myers","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"CHRIS MYERS","raw_affiliation_strings":["University of Utah, Salt Lake City, UT 84112, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, UT 84112, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050136674","display_name":"Alper \u015een","orcid":"https://orcid.org/0000-0002-5508-6484"},"institutions":[{"id":"https://openalex.org/I4405392","display_name":"Bo\u011fazi\u00e7i University","ror":"https://ror.org/03z9tma90","country_code":"TR","type":"education","lineage":["https://openalex.org/I4405392"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"ALPER SEN","raw_affiliation_strings":["Bogazici University, Istanbul, Turkey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bogazici University, Istanbul, Turkey","institution_ids":["https://openalex.org/I4405392"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.0363,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.91589219,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"21","issue":"02","first_page":"191","last_page":"210"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.7751791477203369},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7392551898956299},{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.6458836793899536},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6257414221763611},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5605596899986267},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5352334380149841},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5283587574958801},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4583984315395355},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4210098385810852},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.41348108649253845},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2465209662914276},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20926478505134583},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18371990323066711},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13987919688224792},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10481739044189453},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08763957023620605}],"concepts":[{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.7751791477203369},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7392551898956299},{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.6458836793899536},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6257414221763611},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5605596899986267},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5352334380149841},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5283587574958801},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4583984315395355},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4210098385810852},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.41348108649253845},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2465209662914276},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20926478505134583},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18371990323066711},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13987919688224792},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10481739044189453},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08763957023620605},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1142/s0129054110007209","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0129054110007209","pdf_url":null,"source":{"id":"https://openalex.org/S68047077","display_name":"International Journal of Foundations of Computer Science","issn_l":"0129-0541","issn":["0129-0541","1793-6373"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Foundations of Computer Science","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.107.5522","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.107.5522","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.async.ece.utah.edu/publications/ATVA07b.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.493.6247","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.493.6247","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cmpe.boun.edu.tr/~sen/publications/ijfcs10.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W94695219","https://openalex.org/W1483606732","https://openalex.org/W1538215585","https://openalex.org/W1570732927","https://openalex.org/W1595871524","https://openalex.org/W1599033249","https://openalex.org/W1676597814","https://openalex.org/W1995691455","https://openalex.org/W2084777069","https://openalex.org/W2120953717","https://openalex.org/W2134451579","https://openalex.org/W2144785157","https://openalex.org/W2147115528","https://openalex.org/W2157658705","https://openalex.org/W2168621995","https://openalex.org/W2338031113","https://openalex.org/W3148137902"],"related_works":["https://openalex.org/W2051409810","https://openalex.org/W2540848379","https://openalex.org/W1533355605","https://openalex.org/W1996609773","https://openalex.org/W2003299602","https://openalex.org/W2003204375","https://openalex.org/W4290994271","https://openalex.org/W2268772050","https://openalex.org/W129691771","https://openalex.org/W1994364444"],"abstract_inverted_index":{"Verification":[0],"of":[1,10,17,44],"analog/mixed-signal":[2],"(AMS)":[3],"circuits":[4],"is":[5],"complicated":[6],"by":[7],"the":[8,42,45],"difficulty":[9],"obtaining":[11],"circuit":[12],"models":[13,27],"at":[14],"suitable":[15,28],"levels":[16],"abstraction.":[18],"We":[19],"propose":[20],"a":[21,49],"method":[22],"to":[23,48],"automatically":[24],"generate":[25],"abstract":[26],"for":[29],"formal":[30],"verification":[31],"and":[32,53],"system-level":[33],"simulation":[34,37],"from":[35],"transistor-level":[36],"traces.":[38],"This":[39],"paper":[40],"discusses":[41],"application":[43],"proposed":[46],"methodology":[47],"switched":[50],"capacitor":[51],"integrator":[52],"PLL":[54],"phase":[55],"detector.":[56]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}